R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1071

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
18.3.3
ADCSR_1 controls A/D conversion operations.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
4
Bit Name
ADF
ADIE
ADST
EXCKS
A/D Control/Status Register for Unit 1 (ADCSR_1)
Initial
Value
0
0
0
0
R/W
R/(W)* A/D End Flag
R/W
R/W
R/W
A/D Interrupt Enable
Description
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Setting this bit to 1 enables ADI interrupts by ADF.
A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters wait state.
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when A/D conversion
on the specified channel ends. In scan mode, A/D
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or hardware standby mode. While the ADSTCLR bit in
ADCR is set to 1, the ADST bit is cleared to 0
automatically when A/D conversion on all selected
channels ends, and then A/D conversion stops.
The timing to clear the ADST bit automatically differs
from that of ADF setting; the ADST bit is cleared before
the ADF bit is set.
Clock Extension Select
Specifies the A/D conversion time in combination with the
CKS1 and CKS0 bits in ADCR. Be sure to set these
three bits at one time. For details, see the description of
the ADCR resisters.
Completion of A/D conversion in single mode
Completion of A/D conversion on all specified
channels in scan mode
Writing of 0 after reading ADF = 1
Reading from ADDR after activation of the DTC by an
ADI interrupt
Section 18 A/D Converter
Page 1041 of 1448