R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1245
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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H8S/2427, H8S/2427R, H8S/2425 Group
25.4
25.4.1
1. The following points should be noted since the frequency of φ changes according to the
2. All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
3. Note that the frequency of φ will be changed when setting PLLCR while executing the external
25.4.2
Since various characteristics related to the resonator are closely linked to the user’s board design,
thorough evaluation is necessary on the user’s part, using the resonator connection examples
shown in this section as a guide. As the parameters for the oscillation circuit will depend on the
floating capacitance of the resonator and the user board, the parameters should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the resonator pin.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
settings of PLLCR.
Select a clock division ratio that is within the operation guaranteed range of clock cycle time
tcyc shown in the AC timing of the Electrical Characteristics. In other words, φ must be set to
a value between 8 MHz (minimum) and 33 MHz (maximum). The setting of φ must not be less
than 8 MHz or greater than 33 MHz.
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software
Standby Mode in section 26.2.3, Software Standby Mode, for details.
bus cycle with the write-data-buffer function.
Usage Notes
Notes on Clock Pulse Generator
Notes on Resonator
Section 25 Clock Pulse Generator
Page 1215 of 1448
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