R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet

H8S/2427, H8S/2427R, H8S/2425 Group 16 Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

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Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating the MCU. A basic knowledge ...

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Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...

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Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...

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Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator INT Interrupt controller SCI Serial communication interface TMR 8-bit timer TPU 16-bit ...

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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Specifications....................................................................................... 2 1.2 List of Products.................................................................................................................... 10 1.3 Block Diagrams ................................................................................................................... 13 1.4 Pin Description .................................................................................................................... 15 1.4.1 Pin Assignments ..................................................................................................... 15 1.4.2 Pin Assignments in Each Operating ...

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Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 76 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 76 2.7.5 Absolute Address—@aa:8 /@aa:16 / @aa:24 /@aa:32.......................................... 76 2.7.6 Immediate—#xx:8 / #xx:16/ #xx:32....................................................................... 77 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, ...

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Reset Exception Handling .................................................................................... 106 5.3.2 Interrupts after Reset............................................................................................. 108 5.3.3 On-Chip Peripheral Functions after Reset Release............................................... 108 5.4 Trace Exception Handling ................................................................................................. 109 5.5 Interrupt Exception Handling ............................................................................................ 110 5.6 Trap Instruction Exception Handling................................................................................. 111 5.7 Illegal Instruction ...

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Section 7 Bus Controller (BSC) ........................................................................ 155 7.1 Features.............................................................................................................................. 155 7.2 Input/Output Pins............................................................................................................... 158 7.3 Register Descriptions ......................................................................................................... 161 7.3.1 Bus Width Control Register (ABWCR)................................................................ 162 7.3.2 Access State Control Register (ASTCR) .............................................................. 162 7.3.3 Wait Control Registers AH, AL, ...

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Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 225 7.7 DRAM Interface ................................................................................................................ 227 7.7.1 Setting DRAM Space............................................................................................ 227 7.7.2 Address Multiplexing ........................................................................................... 228 7.7.3 Data Bus ............................................................................................................... 228 7.7.4 Pins Used for DRAM Interface............................................................................. 229 7.7.5 ...

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Bus Release........................................................................................................................ 313 7.12.1 Operation .............................................................................................................. 313 7.12.2 Pin States in External Bus Released State ............................................................ 314 7.12.3 Transition Timing ................................................................................................. 315 7.13 Bus Arbitration .................................................................................................................. 317 7.13.1 Operation .............................................................................................................. 317 7.13.2 Bus Transfer Timing............................................................................................. 318 7.14 Bus Controller ...

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Operation ........................................................................................................................... 368 8.5.1 Transfer Modes..................................................................................................... 368 8.5.2 Sequential Mode ................................................................................................... 370 8.5.3 Idle Mode.............................................................................................................. 374 8.5.4 Repeat Mode......................................................................................................... 378 8.5.5 Single Address Mode............................................................................................ 383 8.5.6 Normal Mode........................................................................................................ 387 8.5.7 Block Transfer Mode ............................................................................................ 391 8.5.8 Basic Bus Cycles ...

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Examples of Operation Timing in Each Mode ..................................................... 479 9.4.12 Ending EXDMA Transfer..................................................................................... 493 9.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 494 9.5 Interrupt Sources................................................................................................................ 495 9.6 Usage Notes ....................................................................................................................... 497 Section 10 Data Transfer Controller (DTC)......................................................499 ...

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Usage Notes ....................................................................................................................... 533 10.8.1 Module Stop Function Setting .............................................................................. 533 10.8.2 On-Chip RAM ...................................................................................................... 533 10.8.3 Transfer Information Start Address ...................................................................... 533 10.8.4 DTCE Bit Setting.................................................................................................. 533 10.8.5 DMAC Transfer End Interrupt.............................................................................. 533 10.8.6 Chain Transfer ...................................................................................................... 534 ...

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Port 6 Open Drain Control Register (P6ODR) ..................................................... 619 11.6.5 Pin Functions ........................................................................................................ 619 11.7 Port 8.................................................................................................................................. 624 11.7.1 Port 8 Data Direction Register (P8DDR).............................................................. 624 11.7.2 Port 8 Data Register (P8DR)................................................................................. 625 11.7.3 Port 8 Register (PORT8)....................................................................................... 625 ...

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Port D Open Drain Control Register (PDODR).................................................... 682 11.12.6 Pin Functions ........................................................................................................ 683 11.12.7 Port D Input Pull-Up MOS States......................................................................... 684 11.13 Port E ................................................................................................................................. 685 11.13.1 Port E Data Direction Register (PEDDR)............................................................. 685 11.13.2 Port E Data Register ...

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Port Function Control Register 4 (PFCR4)........................................................... 734 11.18.6 Port Function Control Register 5 (PFCR5)........................................................... 736 Section 12 16-Bit Timer Pulse Unit (TPU) ....................................................... 737 12.1 Features.............................................................................................................................. 737 12.2 Input/Output Pins............................................................................................................... 744 12.3 Register Descriptions ......................................................................................................... 747 12.3.1 Timer Control ...

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Contention between TGR Read and Input Capture............................................... 831 12.10.9 Contention between TGR Write and Input Capture.............................................. 832 12.10.10 Contention between Buffer Register Write and Input Capture.......................... 833 12.10.11 Contention between Overflow/Underflow and Counter Clearing...................... 834 12.10.12 Contention between TCNT ...

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Operation ........................................................................................................................... 873 14.3.1 Pulse Output.......................................................................................................... 873 14.3.2 Reset Input ............................................................................................................ 874 14.4 Operation Timing............................................................................................................... 875 14.4.1 TCNT Incrementation Timing .............................................................................. 875 14.4.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 876 14.4.3 Timing of Timer Output ...

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Changing Value of CKS2 to CKS0 ...................................................................... 898 15.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 898 15.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 899 15.6.6 System Reset by WDTOVF Signal....................................................................... 899 Section 16 Serial Communication Interface ...

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Data Format (Except for Block Transfer Mode)................................................... 962 16.7.3 Block Transfer Mode ............................................................................................ 963 16.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 964 16.7.5 Initialization.......................................................................................................... 966 16.7.6 Data Transmission (Except for Block Transfer Mode)......................................... 967 16.7.7 Serial Data ...

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Operation ......................................................................................................................... 1011 2 17.4 Bus Format.................................................................................................... 1011 17.4.2 Master Transmit Operation................................................................................. 1012 17.4.3 Master Receive Operation .................................................................................. 1014 17.4.4 Slave Transmit Operation ................................................................................... 1017 17.4.5 Slave Receive Operation..................................................................................... 1020 17.4.6 Noise Canceler.................................................................................................... 1022 17.4.7 Example of ...

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Section 19 D/A Converter ...............................................................................1067 19.1 Features............................................................................................................................ 1067 19.2 Input/Output Pins............................................................................................................. 1069 19.3 Register Descriptions ....................................................................................................... 1069 19.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)........................................... 1069 19.3.2 D/A Control Register 23 (DACR23) .................................................................. 1070 19.4 Operation ......................................................................................................................... 1072 ...

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Register Description ........................................................................................................ 1119 21.3.1 FSI Control Register 1 (FSICR1) ....................................................................... 1120 21.3.2 FSI Control Register 2 (FSICR2) ....................................................................... 1122 21.3.3 FSI Byte Count Register (FSIBNR) ................................................................... 1123 21.3.4 FSI Instruction Register (FSIINS) ...................................................................... 1124 21.3.5 FSI Status Register ...

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Lock Bit Program ............................................................................................... 1155 23.6.8 Read Lock Bit Data ............................................................................................ 1156 23.7 Data Protection Function ................................................................................................. 1157 23.8 Status Register ................................................................................................................. 1158 23.8.1 Sequencer Status (FMRDY Bit) ......................................................................... 1159 23.8.2 Erase Status (FMERSF Bit) ................................................................................ 1159 23.8.3 Programming ...

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Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) ........................................................................ 1225 26.1.4 RAM Module Stop Control Registers H and L (RMMSTPCRH, RMMSTPCRL)....................................................................... 1226 26.2 Operation ......................................................................................................................... 1228 26.2.1 Clock Division Mode.......................................................................................... 1228 26.2.2 Sleep Mode ......................................................................................................... 1229 26.2.3 ...

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D/A Conversion Characteristics ......................................................................... 1329 28.2.6 Flash Memory Characteristics ............................................................................ 1330 28.3 Timing Charts (3-V Version)........................................................................................... 1331 28.3.1 Clock Timing ...................................................................................................... 1331 28.3.2 Control Signal Timing ........................................................................................ 1333 28.3.3 Bus Timing ......................................................................................................... 1334 28.3.4 DMAC and EXDMAC Timing........................................................................... 1354 ...

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H8S/2427, H8S/2427R, H8S/2425 Group 1.1 Features The H8S/2427 Group, H8S/2427R Group, and H8S/2425 Group are CISC (Complex Instruction Set Computer) microprocessors that integrate an H8S/2600 CPU core, which has an internal 16-bit architecture and is upward-compatible with Renesas original H8/300, ...

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Section 1 Overview 1.1.2 Overview of Specifications The specifications of this LSI are summarized in table 1.1. Table 1.1 Overview of Specifications Module/ Type Function Memory ROM RAM CPU CPU Operating mode Page 2 of 1448 Description • Expanded ROM: ...

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H8S/2427, H8S/2427R, H8S/2425 Group Module/ Type Function CPU MCU operating mode Interrupts Interrupt (sources) controller REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 Description • Mode 1: Expanded mode with on-chip ROM disabled, 16-bit bus (MD2 and MD1 pins are low and ...

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Section 1 Overview Module/ Type Function DMA DMA controller (DMAC) EXDMA controller (EXDMAC) Data transfer controller (DTC) Page 4 of 1448 Description • DMA transfer is possible on six channels • Three activation sources (auto-request, on-chip module interrupt, and external ...

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H8S/2427, H8S/2427R, H8S/2425 Group Module/ Type Function External bus Bus controller extension (BSC) Clock Clock pulse generator (CPG) REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 Description • External address space: 16 Mbytes • Manages the external address space divided into eight ...

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Section 1 Overview Module/ Type Function A/D A/D converter converter (ADC) D/A D/A converter converter (DAC) Page 6 of 1448 Description • Two units • 10-bit resolution • Number of input channels H8S/2427 Group and H8S/2427R Group: 16 channels ⎯ ...

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H8S/2427, H8S/2427R, H8S/2425 Group Module/ Type Function Timer 16-bit timer pulse unit (TPU) 8-bit timer (TMR) Programmable pulse generator (PPG) Watchdog Watchdog timer timer (WDT) REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 Description • 16-bit timer × 12 channels (general pulse ...

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Section 1 Overview Module/ Type Function Serial Serial interface communi- cation interface (SCI) Smart Card/SIM 2 High bus function interface 2 communi- (IIC2) cations Synchronous serial communi- cation unit (SSU) High-speed FSI interface communi- (FSI) cation Page 8 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Type I/O ports Package Operating frequency/ power supply voltage Operating environment temperature (°C) REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 Description H8S/2427 Group, H8S/2427R Group: • Input-only pins: 18 (PLQP0144KA-A) 17 (PTLG0145JB-A) • Input/output pins: 98 • ...

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... Table 1.2 Product Code Lineup Product Type Part No. H8S/2427R R4F24279NVRFQU Group R4F24278NVRFQU R4F24276NVRFQU R4F24275NVRFQU R4F24279DVRFQU R4F24278DVRFQU R4F24276DVRFQU R4F24275DVRFQU H8S/2427 R4F24279NVFQU Group R4F24278NVFQU R4F24276NVFQU R4F24275NVFQU R4F24279NFQU R4F24278NFQU R4F24276NFQU R4F24275NFQU R4F24279DVFQU R4F24278DVFQU R4F24276DVFQU R4F24275DVFQU R4F24279DFQU R4F24278DFQU R4F24276DFQU R4F24275DFQU Page 10 of 1448 Flash Memory ...

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H8S/2427, H8S/2427R, H8S/2425 Group Product Type Part No. H8S/2425 R4F24259NVFPU Group R4F24258NVFPU R4F24256NVFPU R4F24255NVFPU R4F24259NFPU R4F24258NFPU R4F24256NFPU R4F24255NFPU R4F24259DVFPU R4F24258DVFPU R4F24256DVFPU R4F24255DVFPU R4F24259DFPU R4F24258DFPU R4F24256DFPU R4F24255DFPU R4F24259NVFAU R4F24258NVFAU R4F24256NVFAU R4F24255NVFAU R4F24259NFAU R4F24258NFAU R4F24256NFAU R4F24255NFAU R4F24259DVFAU R4F24258DVFAU R4F24256DVFAU R4F24255DVFAU R4F24259DFAU R4F24258DFAU ...

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Section 1 Overview Product type name 2427 Figure 1.1 Meaning of Product Type Name Page 12 of 1448 Indicates treatment of outer leads U: Sn Indicates the package FQ: PLQP0144KA-A FP: ...

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H8S/2427, H8S/2427R, H8S/2425 Group 1.3 Block Diagrams MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR /SSO0 PF2/LCAS /DQML /IRQ15-A /SSI0-C PF1/UCAS *2 /DQMU *1 /IRQ14-A /SSCK0-C PF0/WAIT-A /ADTRG0-B/SCS0-C PG6/BREQ-A PG5/BACK-A PG4/BREQO-A ...

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Section 1 Overview MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS * /SSI0-C PF1/CS5/UCAS * /SSCK0-C PF0/WAIT-A/OE-A * /ADTRG0-B /SCS0-C PG6/BREQ-A PG5/BACK-A PG4/BREQO-A/CS4 PG3/CS3/RAS3 * PG2/CS2/RAS2 * PG1/CS1 PG0/CS0 P85/PO5-B/TIOCB4-B/TMO1-B/SCK3/TIOCA9-B P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 ...

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H8S/2427, H8S/2427R, H8S/2425 Group 1.4 Pin Description 1.4.1 Pin Assignments 4 1 PG2/CS2/RAS2 * /RAS * 109 1 4 PG3/CS3/RAS3 * /CAS * 110 AVcc 111 Vref 112 P40/AN0_0 113 P41/AN1_0 114 P42/AN2_0 115 P43/AN3_0 116 P44/AN4_0 117 P45/AN5_0 118 ...

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Section 1 Overview PG2/CS2/RAS2* PG3/CS3/RAS3 Vref P40/IRQ0-B/AN0_0 P41/IRQ1-B/AN1_0 P42/IRQ2-B/AN2_0 P43/IRQ3-B/AN3_0 P44/IRQ4-B/AN4_0 P45/IRQ5-B/AN5_0 P46/IRQ6-B/AN6_0 P47/IRQ7-B/AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AV SS PG4/BREQO-A/CS4 /ETCK * PG5/BACK-A /ETMS * PG6/BREQ-A /ETDI * P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A /ETRST * P35/OE-B* /SCK1/SCL0 3 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Vss MD1 MD0 B MD2 Vcc P31 C PC0 P80 PC1 D PC4 PC2 PC3 E PC7 Vss PC5 F PB3 PC6 PB1 G PB6 PB2 PA0 H Vss PB7 PA3 J ...

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Section 1 Overview 1.4.2 Pin Assignments in Each Operating Mode Table 1.3 Pin Assignments in Each Operating Mode of H8S/2427 Group and H8S/2427R Group Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode MD2 2 A1 Vss 3 C2 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode A15 23 G3 A16 24 J4 A17 25 H1 Vss 26 J2 A18 27 H3 A19 28 K4 A20/IRQ4 PA5/A21/FSICK IRQ5-A/SSCK0 PA6/A22/FSIDI ...

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Section 1 Overview Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode 1 WDTOVF 39 M3 NMI VCL 42 N3 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA ...

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H8S/2427, H8S/2427R, H8S/2425 Group Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4 P25/WAIT-B/ IRQ13-B/ PO5-A/TIOCB4 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ADTRG1 58 K7 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 59 K8 P83/IRQ3-B/ PO3-B/ TIOCD3-B/ TMCI1-B/RxD3/ ETEND3 ...

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Section 1 Overview Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode 1 70 M11 Vss 71 N11 PE7/D7/AD7 72 N12 Vcc 73 M13 D8/AD8 74 N13 D9/AD9 75 L12 D10/AD10 76 M12 D11/AD11 77 L11 D12/AD12 78 L13 D13/AD13 79 K12 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode G12 90 G10 PF6/AS/AH 91 H13 PLLVcc RES 92 G11 93 G13 PLLVss 94 F10 PF7/φ 95 F11 Vss 96 F12 XTAL 97 F13 EXTAL 98 ...

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Section 1 Overview Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode 1 112 B12 Vref 113 A11 P40/AN0_0 114 C11 P41/AN1_0 115 B10 P42/AN2_0 116 C10 P43/AN3_0 117 A10 P44/AN4_0 118 B9 P45/AN5_0 119 C9 P46/AN6_0 120 B8 P47/AN7_0 121 A9 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Pin No. PTLG0145JB-A PLQP0144KA-A (in Planning) Mode 1 135 C6 P52/BACK-B/ IRQ2-A/PO4-B/ TIOCA4-B/ TMO0-B/SCK2 136 D4 P53/IRQ3-A/ ADTRG0-A 137 A5 P35/OE-B* CKE-B* SCL0 138 B4 P34/SCK0/ SCK4-A/SDA0 139 C5 P33/RxD1/SCL1 140 A4 P32/RxD0/IrRxD/ SDA1 141 B3 ...

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Section 1 Overview Table 1.4 Pin Assignments in Each Operating Mode of H8S/2425 Group Pin No. PLQP0120LA-A PLQP0120KA-A Mode 1 Mode 2 1 MD2 MD2 2 Vcc Vcc ...

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H8S/2427, H8S/2427R, H8S/2425 Group Pin No. PLQP0120LA-A PLQP0120KA-A Mode 1 Mode 2 26 A20/IRQ4-A A20/IRQ4-A 27 PA5/A21/IRQ5-A/ PA5/A21/IRQ5-A/ SSCK0-B/FSICK SSCK0-B/FSICK 28 PA6/A22/IRQ6-A/ PA6/A22/IRQ6-A/ SSI0-B/FSIDI SSI0-B/FSIDI 29 PA7/A23/CS7/ PA7/A23/CS7/ IRQ7-A/SSO0-B/ IRQ7-A/SSO0-B/ FSIDO FSIDO 30 EMLE EMLE WDTOVF WDTOVF 31 NMI NMI ...

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Section 1 Overview Pin No. PLQP0120LA-A PLQP0120KA-A Mode 1 Mode 2 41 P17/PO15/ P17/PO15/ TIOCB2/TCLKD/ TIOCB2/TCLKD/ SCS0-A SCS0-A 42 P20/PO0-A/ P20/PO0-A/ TIOCA3-A/ TIOCA3-A/ TMRI0-A TMRI0-A 43 P21/PO1-A/ P21/PO1-A/ TIOCB3-A/ TIOCB3-A/ TMRI1-A TMRI1-A 44 P22/PO2-A/ P22/PO2-A/ TIOCC3-A/ TIOCC3-A/ TMCI0-A TMCI0-A 45 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Pin No. PLQP0120LA-A PLQP0120KA-A Mode 1 Mode 2 57 PE6/D6/AD6 PE6/D6/AD6 58 Vss Vss 59 PE7/D7/AD7 PE7/D7/AD7 60 Vcc Vcc 61 D8/AD8 D8/AD8 62 D9/AD9 D9/AD9 63 D10/AD10 D10/AD10 64 D11/AD11 D11/AD11 65 D12/AD12 D12/AD12 66 ...

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Section 1 Overview Pin No. PLQP0120LA-A PLQP0120KA-A Mode 1 Mode 2 84 Vcc Vcc 85 P83/PO3-B/ P83/PO3-B/ TIOCD3-B/ TIOCD3-B/ TMCI1-B/RxD3 TMCI1-B/RxD3 86 P81/PO1-B/ P81/PO1-B/ TIOCB3-B/ TIOCB3-B/ TMRI1-B/TxD3 TMRI1-B/TxD3 87 Vss Vss STBY STBY 88 89 PG0/CS0 PG0/CS0 90 PG1/CS1 PG1/CS1 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Pin No. PLQP0120LA-A PLQP0120KA-A Mode 1 Mode 2 109 P50/BREQO-B/ P50/BREQO-B/ IRQ0-A/PO0-B/ IRQ0-A/ TIOCA3-B/ PO0-B/TIOCA3-B/ TMRI0-B/TxD2/ TMRI0-B/TxD2/ SDA3 SDA3 110 P51/BREQ-B/ P51/BREQ-B/ IRQ1-A/PO2-B/ IRQ1-A/PO2-B/ TIOCC3-B/ TIOCC3-B/ TMCI0-B/RxD2/ TMCI0-B/RxD2/ SCL3 SCL3 111 P52/BACK-B/ P52/BACK-B/ IRQ2-A/PO4-B/ IRQ2-A/PO4-B/ TIOCA4-B/ ...

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Section 1 Overview 1.4.3 Pin Functions Table 1.5 Pin Functions H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A Power V 4, 72, 98, CC supply 10, 18, SS 25, 50, 70, 95, 102 PLLV 91 CC PLLV 93 SS VCL ...

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H8S/2427, H8S/2427R, H8S/2425 Group H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A Operating MD2 1 mode MD1 144 control MD0 143 RES System 92 control STBY 103 EMLE 32 Address A23 26, bus 11, ...

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Section 1 Overview H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A CS7 to Bus 38 to 35, CS0 control 110 to 107 HWR 88 LWR 87 BREQ-A 132 BREQ-B 134 BREQO-A 130 BREQO-B 133 BACK-A 131 BACK-B ...

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H8S/2427, H8S/2427R, H8S/2425 Group H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A 1 Bus DQMU* 85 control 1 DQML* 86 RAS2* 3 109 RAS3* 3 110 RAS4 RAS5 RAS* 1 109 CAS* 1 110 WE* ...

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Section 1 Overview H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A NMI Interrupt 40 signals IRQ15-A to 86, 85, IRQ8-A* 2 106 to 104 IRQ7 28, IRQ0-A 136 to 133 IRQ15 IRQ8-B* 2 ...

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H8S/2427, H8S/2427R, H8S/2425 Group H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A EDREQ3 EXDMA 33 controller EDREQ2 3 (EXDMAC) ETEND3 ETEND2 34 EDACK3 61 EDACK2 60 EDRAK3 49 EDRAK2 48 16-bit timer TCLKH 22 pulse TCLKG 20 unit (TPU) TCLKF ...

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Section 1 Overview H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A 16-bit timer TIOCA3-A 51 pulse TIOCB3-A 52 unit (TPU) TIOCC3-A 53 TIOCD3-A 54 TIOCA3-B 133 TIOCB3-B 33 TIOCC3-B 134 TIOCD3-B 59 TIOCA4-A 55 TIOCB4-A 56 TIOCA4-B 135 TIOCB4-B 61 TIOCA5 57 TIOCB5 ...

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H8S/2427, H8S/2427R, H8S/2425 Group H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A 16-bit timer TIOCA11 12 pulse TIOCB11 13 unit (TPU) Program- PO15 mable PO8 pulse PO7 generator (PPG) PO6 PO5-A to PO0-A PO5-B 61 PO4-B ...

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Section 1 Overview H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A Serial TxD4-A 54 commu- TxD4-B 24 nication TxD3 33 interface (SCI)/ TxD2 133 Smart Card TxD1 141 interface (SCI_0 TxD0/ 142 with IrDA IrTxD function) RxD4-A 55 RxD4-B 26 RxD3 59 RxD2 ...

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H8S/2427, H8S/2427R, H8S/2425 Group H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A Synchro- SSO0-A 46 nous serial SSO0-B 31 commu- SSO0-C 87 nication unit (SSU) SSI0-A 47 SSI0-B 30 SSI0-C 86 SSCK0-A 48 SSCK0-B 29 SSCK0-C 85 SCS0-A 49 SCS0-B 28 SCS0-C 84 ...

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Section 1 Overview H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A D/A DA3 126 converter DA2 125 A/D AV 111 CC converter, D/A converter AV 129 SS Vref 112 I/O ports P17 to P10 P27 to P20 ...

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H8S/2427, H8S/2427R, H8S/2425 Group H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A I/O ports P85 61 2 P84* 60 P83 59 2 P82* 34 P81 33 2 P80 P97* , 128 to 121 2 P96* , P95, P94, P93 to 2 ...

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Section 1 Overview H8S/2427, H8S/2427R Type Symbol PLQP0144KA-A I/O ports PG6 to 132 to 130, PG0 110 to 107 PH3 PH0 PJ2 PJ1* 101 2 PJ0* 100 Notes: 1. Not ...

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H8S/2427, H8S/2427R, H8S/2425 Group The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear ...

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Section 2 CPU 16 ÷ 8-bit register-register divide: 12 states 16 × 16-bit register-register multiply: 3 states 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes Normal mode* Advanced mode Note: * Normal mode is not available ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • ...

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Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register One 8-bit and two 32-bit control registers have been added. • Enhanced instructions Addressing ...

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Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the ...

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H8S/2427, H8S/2427R, H8S/2425 Group H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode) SP (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used not stored ...

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Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers the upper 16-bit ...

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H8S/2427, H8S/2427R, H8S/2425 Group The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode ...

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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC bit extended ...

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Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...

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H8S/2427, H8S/2427R, H8S/2425 Group SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC ...

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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...

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H8S/2427, H8S/2427R, H8S/2425 Group Bit Bit Name Initial Value 2 Z Undefined 1 V Undefined 0 C Undefined 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32- bit registers denoted MACH ...

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Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...

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H8S/2427, H8S/2427R, H8S/2425 Group Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB Legend: ERn : General register General register General register R RnH : General ...

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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* LDM, STM MOVFPE* ...

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Section 2 CPU 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.1 Table of Instructions ...

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H8S/2427, H8S/2427R, H8S/2425 Group Symbol Description → Move ∼ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers ( E7), ...

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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L Performs addition or subtraction on data in two general registers SUB immediate data and ...

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H8S/2427, H8S/2427R, H8S/2425 Group Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and ...

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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ...

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H8S/2427, H8S/2427R, H8S/2425 Group Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit ...

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Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result ...

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H8S/2427, H8S/2427R, H8S/2425 Group Table 2.8 Branch Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS ...

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Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function ⎯ TRAPA Starts trap-instruction exception handling. ⎯ RTE Returns from an exception-handling routine. ⎯ SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC ...

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H8S/2427, H8S/2427R, H8S/2425 Group Table 2.10 Block Data Transfer Instructions Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B else next; ⎯ ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set ...

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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) Page ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register ...

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Section 2 CPU 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum ...

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H8S/2427, H8S/2427R, H8S/2425 Group Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: * Not available in this LSI. 2.7.6 Immediate—#xx:8 / #xx:16/ ...

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Section 2 CPU In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. ...

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Section 2 CPU Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. Page 80 of 1448 H8S/2427, H8S/2427R, H8S/2425 Group Effective Address Calculation PC contents ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The ...

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Section 2 CPU Bus-released state Exception handling state RES = High Reset state * 1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin goes low. A ...

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H8S/2427, H8S/2427R, H8S/2425 Group 2.9 Usage Note 2.9.1 Usage Notes on Bit-wise Operation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the ...

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Section 2 CPU Page 84 of 1448 H8S/2427, H8S/2427R, H8S/2425 Group REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2427 Group and H8S/2425 Group have six operating modes (modes and 7). The operating mode is selected by the setting of the mode ...

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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of ...

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H8S/2427, H8S/2427R, H8S/2425 Group Bit Bit Name Initial Value ⎯ FLSHE 0 ⎯ ⎯ 1 EXPE 0 RAME 1 REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 R/W Descriptions R/W Reserved The initial value should not be ...

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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports function as an address bus, ports D and ...

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H8S/2427, H8S/2427R, H8S/2425 Group 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports ...

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Section 3 MCU Operating Modes 3.3.7 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Port Mode 1 Port A PA7 to PA5 P*/A PA4 to PA0 A Port ...

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H8S/2427, H8S/2427R, H8S/2425 Group 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.6 show memory maps in each operating mode. (Expanded mode with on-chip ROM disabled) H'000000 H'FD8000 H'FEC000 On-chip RAM/External address space/ H'FF0000 On-chip RAM/External address space ...

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Section 3 MCU Operating Modes RAM: 64 Kbytes/48 Kbytes (Expanded mode with on-chip ROM enabled) H'000000 H'080000 H'F00000 H'F02000 H'FD8000 H'FEC000 On-chip RAM/External address space/ H'FF0000 On-chip RAM/External address space* H'FFC000 H'FFD000 H'FFE800 H'FFF800 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. This ...

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H8S/2427, H8S/2427R, H8S/2425 Group H'000000 H'080000 H'F00000 H'F02000 H'FD8000 H'FEC000 H'FF0000 H'FFC000 H'FFD000 H'FFE800 H'FFF800 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR This ...

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Section 3 MCU Operating Modes RAM: 64 Kbytes/48 Kbytes (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FD8000 H'FEC000 On-chip RAM/External address space/ H'FF0000 On-chip RAM/External address space H'FFC000 H'FFD000 External address space H'FFE800 H'FFF800 Internal I/O registers ...

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H8S/2427, H8S/2427R, H8S/2425 Group RAM: 64 Kbytes/48 Kbytes (Expanded mode with on-chip ROM enabled) H'000000 H'060000 H'080000 External address space H'F00000 H'F02000 External address space H'FD8000 H'FEC000 On-chip RAM/External address space/ H'FF0000 On-chip RAM/External address space* H'FFC000 H'FFD000 External address ...

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Section 3 MCU Operating Modes H'000000 H'060000 H'080000 H'F00000 H'F02000 H'FD8000 H'FEC000 H'FF0000 H'FFC000 H'FFD000 H'FFE800 H'FFF800 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. ...

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H8S/2427, H8S/2427R, H8S/2425 Group 4.1 Types of Resets There are two types of resets: a pin reset, and watchdog timer reset. Table 4.1 shows the reset names and sources. The internal state and pins are initialized by a reset. Figure ...

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Section 4 Resets Note that some registers are not initialized by any of the resets. The following describes the CPU internal registers. The PC, one of the CPU internal registers, is initialized by loading the start address from vector addresses ...

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H8S/2427, H8S/2427R, H8S/2425 Group 4.3 Register Descriptions This LSI has the following registers for resets. Table 4.3 Register Configuration Register Name Timer control/status register Reset control/status register Note: * Data bus width in the upper cell: when writing Data bus ...

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Section 4 Resets 4.3.1 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT of the watchdog timer, and the timer mode. For details on the watchdog timer reset, see section 15, Watchdog Timer (WDT). 4.3.2 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Reset exception handling Figure 4.2 Example of Reset Generation Source Determination Flow REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 No RSTCSR.WOVF = 1 Yes Watchdog timer reset Section 4 Resets Pin reset Page 101 of 1448 ...

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Section 4 Resets Page 102 of 1448 H8S/2427, H8S/2427R, H8S/2425 Group REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Section 5 Exception Handling 5.1 Exception Handling Types and Priority As table 5.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in ...

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Section 5 Exception Handling 5.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 5.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for ...

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H8S/2427, H8S/2427R, H8S/2425 Group Exception Source External interrupt IRQ7 5 IRQ8* 5 IRQ9* IRQ10* IRQ11* IRQ12* External interrupt IRQ13* IRQ14* IRQ15* 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. Not ...

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Section 5 Exception Handling 5.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low ...

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H8S/2427, H8S/2427R, H8S/2425 Group Figures 5.1 and 5.2 show examples of the reset sequence. φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start ...

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Section 5 Exception Handling φ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First ...

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H8S/2427, H8S/2427R, H8S/2425 Group 5.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, ...

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Section 5 Exception Handling 5.5 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The ...

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H8S/2427, H8S/2427R, H8S/2425 Group 5.6 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling ...

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Section 5 Exception Handling 5.7 Illegal Instruction Exception Handling Illegal instruction exception handling starts when the CPU executing an illegal instruction code is detected. Illegal instruction exception handling can be executed at all times in the program execution state. The ...

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H8S/2427, H8S/2427R, H8S/2425 Group 5.8 Stack Status after Exception Handling Figure 5.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal Modes * 2 Advanced Modes Notes: 1. Ignored on return. 2. Normal modes ...

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Section 5 Exception Handling 5.9 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the ...

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H8S/2427, H8S/2427R, H8S/2425 Group Section 6 Interrupt Controller 6.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities ...

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Section 6 Interrupt Controller Figure 6.1 shows a block diagram of the interrupt controller. INTM1, INTM0 INTCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISR ITSR ISCR Internal interrupt sources SWDTEND to FSIRXI Interrupt controller [Legend] ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the interrupt controller. Table 6.1 Pin Configuration Name I/O NMI Input IRQ15-A to IRQ0-A* Input IRQ15-B to IRQ0-B* IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in ...

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Section 6 Interrupt Controller 6.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) • IRQ sense control register H (ISCRH) • IRQ sense control register L (ISCRL) • IRQ enable register (IER) • IRQ ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value ⎯ All 0 5 INTM1 0 4 INTM0 0 3 NMIEG 0 ...

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Section 6 Interrupt Controller 6.3.2 Interrupt Priority Registers (IPRA to IPRN) IPR are fourteen 16-bit readable/writable registers that set priorities (levels for interrupts other than NMI. The correspondence between interrupt sources and IPR settings ...

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H8S/2427, H8S/2427R, H8S/2425 Group Bit Bit Name Initial Value ⎯ IPR6 1 5 IPR5 1 4 IPR4 1 ⎯ IPR2 1 1 IPR1 1 0 IPR0 1 REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 R/W ...

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Section 6 Interrupt Controller 6.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value 15 IRQ15E 0 14 IRQ14E 0 13 IRQ13E 0 12 IRQ12E 0 11 IRQ11E 0 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Bit Bit Name Initial Value 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 Note: These bits are reserved in the H8S/2425 Group. * REJ09B0565-0100 Rev. 1.00 ...

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Section 6 Interrupt Controller 6.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0. • ISCRH (H8S/2427 Group and H8S/2427R Group only) Bit Bit Name Initial ...

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H8S/2427, H8S/2427R, H8S/2425 Group Bit Bit Name Initial Value 9 IRQ12SCB 0 8 IRQ12SCA 0 7 IRQ11SCB 0 6 IRQ11SCA 0 5 IRQ10SCB 0 4 IRQ10SCA 0 REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 R/W Description R/W IRQ12 Sense Control B ...

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Section 6 Interrupt Controller Bit Bit Name Initial Value 3 IRQ9SCB 0 2 IRQ9SCA 0 1 IRQ8SCB 0 0 IRQ8SCA 0 Page 126 of 1448 H8S/2427, H8S/2427R, H8S/2425 Group R/W Description R/W IRQ9 Sense Control B R/W IRQ9 Sense Control ...

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H8S/2427, H8S/2427R, H8S/2425 Group • ISCRL Bit Bit Name Initial Value 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB 0 12 IRQ6SCA 0 11 IRQ5SCB 0 10 IRQ5SCA 0 REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 R/W Description R/W IRQ7 Sense ...

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Section 6 Interrupt Controller Bit Bit Name Initial Value 9 IRQ4SCB 0 8 IRQ4SCA 0 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 Page 128 of 1448 H8S/2427, H8S/2427R, H8S/2425 Group R/W Description R/W IRQ4 Sense ...

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H8S/2427, H8S/2427R, H8S/2425 Group Bit Bit Name Initial Value 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 REJ09B0565-0100 Rev. 1.00 Jul 22, 2010 R/W Description R/W IRQ1 Sense Control B R/W IRQ1 Sense Control A 00: ...

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Section 6 Interrupt Controller 6.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value 2 15 IRQ15F IRQ14F IRQ13F IRQ12F* 0 ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. • H8S/2427 Group and H8S/2427R Group Bit Bit Name Initial Value 15 ITS15 0 14 ITS14 0 13 ITS13 0 12 ITS12 0 ...

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Section 6 Interrupt Controller Bit Bit Name Initial Value 6 ITS6 0 5 ITS5 0 4 ITS4 0 3 ITS3 0 2 ITS2 0 1 ITS1 0 0 ITS0 0 Page 132 of 1448 H8S/2427, H8S/2427R, H8S/2425 Group R/W Description ...

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H8S/2427, H8S/2427R, H8S/2425 Group • H8S/2425 Group Bit Bit Name Initial Value R ⎯ All 0 7 ITS7 0 6 ITS6 0 5 ITS5 0 4 ITS4 0 3 ITS3 0 2 ITS2 0 1 ITS1 0 ...

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Section 6 Interrupt Controller 6.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value 15 SSI15 SSI14 SSI13 ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.4 Interrupt Sources 6.4.1 External Interrupts The H8S/2427 Group and H8S/2427R Group have seventeen external interrupts: NMI and IRQ15 to IRQ0. The H8S/2425 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can ...

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Section 6 Interrupt Controller IRQnSCB, IRQnSCA Edge/level detection circuit IRQn input Note for H8S/2427 Group and H8S/2427R Group for H8S/2425 Group Figure 6.2 Block Diagram of IRQ Interrupts 6.4.2 Internal ...

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H8S/2427, H8S/2427R, H8S/2425 Group Table 6.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Vector Source Source Number External NMI 7 pin IRQ0 16 IRQ1 17 IRQ2 18 IRQ3 19 IRQ4 20 IRQ5 21 IRQ6 22 IRQ7 ...

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Section 6 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number ⎯ Reserved for 36 system use 37 A/D_0 ADI0 38 Reserved for 39 system use TPU_0 TGI0A 40 TGI0B 41 TGI0C 42 TGI0D 43 TCI0V 44 Reserved for ...

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H8S/2427, H8S/2427R, H8S/2425 Group Origin of Interrupt Interrupt Vector Source Source Number TPU_4 TGI4A 64 TGI4B 65 TCI4V 66 TCI4U 67 TPU_5 TGI5A 68 TGI5B 69 TCI5V 70 TCI5U 71 TMR_0 CMIA0 72 CMIB0 73 OVI0 74 Reserved for 75 ...

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Section 6 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number SCI_0 ERI0 88 RXI0 89 TXI0 90 TEI0 91 SCI_1 ERI1 92 RXI1 93 TXI1 94 TEI1 95 SCI_2 ERI2 96 RXI2 97 TXI2 98 TEI2 99 SCI_3 ...

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H8S/2427, H8S/2427R, H8S/2425 Group Origin of Interrupt Interrupt Vector Source Source Number IIC2_0 IICI0 116 Reserved for 117 system use IIC2_1 IICI1 118 Reserved for 119 system use TPU_6 TGI6A 120 TGI6B 121 TGI6C 122 TGI6D 123 TCI6V 124 TPU_7 ...

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Section 6 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number TPU_11 TGI11A 142 TGI11B 143 TCI11V 144 TCI11U 145 ⎯ Reserved for 146 system use 147 148 149 150 151 152 IIC2_2 IICI2 153 IIC2_3 IICI3 154 SSU ...

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H8S/2427, H8S/2427R, H8S/2425 Group Origin of Interrupt Interrupt Vector Source Source Number ⎯ Reserved for 170 system use 171 172 173 174 175 176 177 ⎯ Reserved for 178 system use 179 180 181 182 183 184 185 186 187 ...

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Section 6 Interrupt Controller 6.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in the CPU. Figure 6.3 shows a flowchart of the interrupt acceptance operation ...

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Section 6 Interrupt Controller IRQ0 Figure 6.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Page 146 of 1448 Program execution status Interrupt generated Yes Yes NMI Yes No Yes IRQ1 Yes Save PC ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level ( bits) in the ...

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Section 6 Interrupt Controller Level 7 interrupt Yes Mask level 6 or below Yes Figure 6.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Page 148 of 1448 Program execution status No Interrupt generated Yes Yes NMI No ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.6.3 Interrupt Exception Handling Sequence Figure 6.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...

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Section 6 Interrupt Controller 6.6.4 Interrupt Response Times Table 6.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in ...

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H8S/2427, H8S/2427R, H8S/2425 Group Table 6.5 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch S I Branch address read S J Stack manipulation S K [Legend] m: Number of wait states in an external device access. ...

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Section 6 Interrupt Controller 6.7 Usage Notes 6.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit ...

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H8S/2427, H8S/2427R, H8S/2425 Group 6.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When ...

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Section 6 Interrupt Controller 6.7.5 Change of IRQ Pin Select Register (ITSR) Setting When the ITSR setting is changed, an edge occurs internally and the IRQnF bit* of ISR may be set the unintended timing if the ...

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H8S/2427, H8S/2427R, H8S/2425 Group Section 7 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation ...

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Section 7 Bus Controller (BSC) • Idle cycle insertion Idle cycles can be inserted between external read cycles to different areas Idle cycles can be inserted before the write cycle after a read cycle Idle cycles can be inserted before ...

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H8S/2427, H8S/2427R, H8S/2425 Group 1 EXDMAC address bus* Address selector Internal address bus Internal bus master bus request signal EXDMAC bus request signal* Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal* Internal bus control signals CPU bus request ...

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Section 7 Bus Controller (BSC) 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the bus controller. Table 7.1 Pin Configuration Name Address strobe Address hold Read High write/write enable Low write Chip select 0 Chip select 1 Chip ...

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H8S/2427, H8S/2427R, H8S/2425 Group Name Chip select 4/ row address strobe 4/ 1 write enable* Chip select 5/ row address strobe 5/ 1 SDRAMφ* Chip select 6 Chip select 7 Upper column address strobe/ 1 upper data mask enable* Lower ...

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Section 7 Bus Controller (BSC) Name Data transfer acknowledge 3 (DMAC) Data transfer acknowledge 1 (DMAC) Data transfer acknowledge 0 (DMAC) Data transfer acknowledge 3* (EXDMAC) 3 Data transfer acknowledge 2* (EXDMAC) Notes: 1. Not supported by the 5-V version. ...

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H8S/2427, H8S/2427R, H8S/2425 Group 7.3 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register AH (WTCRAH) • Wait control register AL (WTCRAL) • Wait ...

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Section 7 Bus Controller (BSC) 7.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* 7 ABW7 1/0 6 ABW6 1/0 ...

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H8S/2427, H8S/2427R, H8S/2425 Group 7.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency ...

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