R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 281

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
(3)
In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed
with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR
= H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is
entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller
clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is connected
externally and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in
MSTPCRH.
7.7.13
When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can
be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC
or EXDMAC single address mode at the same time, these bits select whether or not burst access is
to be performed.
Note: The EXDMAC is not supported by the H8S/2425 Group.
(1)
Burst access is performed by determining the address only, irrespective of the bus master. With
the DRAM interface, the DACK or EDACK output goes low from the T
Figure 7.53 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or
EDDS = 1.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Refreshing and All-Module-Clocks-Stopped Mode
When DDS = 1 or EDDS = 1
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
c1
Section 7 Bus Controller (BSC)
state.
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