R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 428

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
8.5.9
(1)
Figure 8.23 shows a transfer example in which TEND output is enabled and byte-size short
address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state
access space to internal I/O space.
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.
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Address bus
Short Address Mode (Channels 0, 1, 2, and 3)
TEND
HWR
LWR
RD
DMA Transfer (Dual Address Mode) Bus Cycles
φ
Bus release
Figure 8.23 Example of Short Address Mode Transfer
DMA
read
DMA
write
Bus release
DMA
read
DMA
write
Bus release
H8S/2427, H8S/2427R, H8S/2425 Group
DMA
read
Last transfer
cycle
REJ09B0565-0100 Rev. 1.00
DMA
write
DMA
dead
Jul 22, 2010
Bus
release