R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 673

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
4
3
2
1
0
Bit Name
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
Initial
Value
0
0
0
0
0
0
0
0
R/W Description
W
W
W
W
W
W
W
W
•
•
Modes 3. 5. 7 (when EXPE = 1) and 4
For pins PA6 to PA0, when the corresponding bit of A22E to
A16E is set to 1, setting a PADDR bit to 1 makes the
corresponding pin an address output, while clearing the bit to
0 makes the corresponding pin an input port. Clearing one of
bits A22E to A16E to 0 makes the corresponding pin an I/O
port, and its function can be switched with PADDR.
When A23E is 1, the PA7 pin functions as an address output
pin when the PA7DDR bit is set to 1, and as an input port
when the bit is cleared to 0.
When A23E is 0, operations differ between the H8S/2427
and H8S/2427R Groups and H8S/2425 Group.
[H8S/2427 Group and H8S/2427R Group]
When the PA7 pin is a general I/O port, the function can be
switched with PA7DDR.
[H8S/2425 Group]
When the CS output enable bit (CS7E) is 1, the PA7 pin
functions as a CS7 output pin when the PA7DDR bit is set to
1, and as an input port when the bit is cleared to 0. When the
CS output enable bit (CS7E) is 0 and the PA7 pin is a
general I/O port, the function can be switched with PA7DDR.
Modes 3, 5, and 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be switched
with PADDR.
Section 11 I/O Ports
Page 643 of 1448