R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 227

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
7.4.4
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 7.7 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
and PFCR0 bits should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when
outputting signals CS0 to CS7.
When areas 2 to 5 are designated as DRAM*
RAS5 signals, respectively. When areas 2 to 5 are designated as continuous DRAM space, CS2
output is used as RAS signal.
When areas 2 to 5 are designated as continuous synchronous DRAM space*
outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and SDRAMφ signals.
Notes: The A23E bit in PFCR1 should be cleared to 0 when CS7 signal is output in the H8S/2425
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
1. The DRAM interface is not supported by the 5-V version.
2. The synchronous DRAM interface is not supported by the H8S/2427 Group and
Group.
Chip Select Signals
H8S/2425 Group.
1
space, outputs CS2 to CS5 are used as RAS2 to
Section 7 Bus Controller (BSC)
2
in the H8S/2427R,
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