R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 326

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
(5)
In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1,
ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas,
for example, if the second read is a full access to DRAM space, only a T
T
Note: The DRAM interface is not supported by the 5-V version.
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 7.82 and 7.83.
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i
cycle is not. The timing in this case is shown in figure 7.81.
Idle Cycle in Case of DRAM Space Access after Normal Space Access
Figure 7.81 Example of DRAM Full Access after External Read
Address bus
Data bus
RD
φ
T
1
External read
T
2
(CAST = 0)
T
3
T
p
DRAM space read
T
r
T
H8S/2427, H8S/2427R, H8S/2425 Group
c1
T
p
c2
cycle is inserted, and a
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010