R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 499

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
(4)
Figure 9.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the EXDMA write cycle, acceptance resumes
after the end of the write cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
Figure 9.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling
edge.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
φ
EDREQ
Address bus
EXDMA control
Channel
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle start; EDREQ pin high level sampling is started at rise of φ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
Figure 9.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge
EDREQ Pin Falling Edge Activation Timing
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
Read
Request clearance period
[3]
Transfer source
EXDMA
read
Write
EXDMA
destination
Transfer
write
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
Read
[6]
Section 9 EXDMA Controller (EXDMAC)
Request clearance period
Transfer source
EXDMA
read
Write
EXDMA
destination
Transfer
write
Idle
Acceptance
resumed
Page 469 of 1448
[7]
Bus release