R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 448

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2427, H8S/2427R, H8S/2425 Group
Section 8 DMA Controller (DMAC)
1
8.5.13
Relation between DMAC and External Bus Requests, Refresh Cycles*
,
2
and EXDMAC*
1
2
When the DMAC accesses external space, contention with a refresh cycle*
, EXDMAC cycle*
, or
external bus release cycle may arise. In this case, the bus controller will suspend the transfer and
1
2
insert a refresh cycle*
, EXDMAC cycle*
, or external bus release cycle, in accordance with the
external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An
external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed
until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
1
2
cycle may be executed at the same time as a refresh cycle*
, EXDMAC cycle*
, or external bus
release cycle.
Notes: 1. Not supported in the 5-V version.
2. Not supported by the H8S/2425 Group.
Page 418 of 1448
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010

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