R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 65

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Type
Bus
control
Symbol
DQMU*
DQML*
RAS2*
RAS3*
RAS4*
RAS5*
RAS*
CAS*
WE*
WAIT-A
WAIT-B
OE-A*
OE-B*
CKE-A*
CKE-B*
1
1
1
3
3
3
3
2
2
1
*
*
1
1
1
3
3
PLQP0144KA-A
85
86
109
110
35
36
109
110
35
84
56
38
137
38
137
H8S/2427, H8S/2427R
PTLG0145JB-A
(in Planning)
H12
H10
A12
A13
L1
M1
A12
A13
L1
J11
N7
M2
A5
M2
A5
Pin No.
H8S/2425
PLQ0120LA-A
PLQP0120KA-A I/O
⎯
⎯
91
92
⎯
⎯
⎯
⎯
⎯
69
47
69
113
⎯
⎯
Output Upper data mask enable signal for
Output Lower-data mask enable signal for
Output Row address strobe signal for the
Output Row address strobe signal for the
Output Column address strobe signal for
Output Write enable signal for the
Input
Output Output enable signal when
Output Clock enable signal when the
Function
accessing the 16-bit continuous
synchronous DRAM space. Also
functions as the data mask enable
signal for accessing the 8-bit
continuous synchronous DRAM
space.
accessing the 16-bit continuous
synchronous DRAM interface
space.
DRAM when the DRAM interface is
set.
Row address strobe signal when
areas 2 to 5 are set as the
continuous DRAM space.
synchronous DRAM when the
synchronous DRAM interface is set.
the synchronous DRAM when the
synchronous DRAM interface is set.
synchronous DRAM when the
synchronous DRAM interface is set.
Requests insertion of a wait state in
the bus cycles when accessing an
external 3-state address space.
accessing the DRAM space.
synchronous DRAM interface is set.
Section 1 Overview
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