R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 392

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
8.3.14
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically and a transfer end signal output, by setting the appropriate bits. The
TEND pin is available only for channels 1 and 3 in short address mode. Except for block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter reaches 0
regardless of the activation source. In block transfer mode, a transfer end signal asserts in the
transfer cycle in which the block size counter reaches 0.
DMATCR can be written to only in common register enabled mode (DMCOMMD = 1).
Page 362 of 1448
Bit
7, 6
5
4
3 to 0
DMA Terminal Control Register (DMATCR)
Bit Name
⎯
TEE1
TEE0
⎯
Initial
Value
All 0
0
0
All 0
R/W
⎯
R/W
R/W
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Transfer End Pin Enable 1
Enables or disables output from the transfer end pin
3 (TEND3) when FAE1 = 0 and from the transfer
end pin 5 (TEND5) when FAE1 = 1.
0: TEND3 or TEND5 pin output is disabled
1: TEND3 or TEND5 pin output is enabled
Transfer End Pin Enable 0
Enables or disables output from the transfer end pin
1 (TEND1) when FAE0 = 0 and from the transfer
end pin 4 (TEND4) when FAE0 = 1.
0: TEND1 or TEND4 pin output is disabled
1: TEND1 or TEND4 pin output is enabled
Reserved
These bits are always read as 0 and cannot be
modified.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010