R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1025

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
This LSI has a four-channel I
The I
interface functions (Rev. 0.3) for standard-mode and fast-mode. The register configuration that
controls the I
Figure 17.1 shows a block diagram of the I
I/O pin connections to external circuits.
17.1
• Continuous transmission/reception
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• Direct bus drive
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
Two pins, SCL and SDA pins function as NMOS open-drain outputs.
2
C bus interface conforms to and provides a subset of the NXP I
Features
2
C bus differs partly from the NXP configuration, however.
Section 17 I
2
C bus interface.
2
C Bus Interface 2 (IIC2)
2
C bus interface 2. Figure 17.2 shows an example of
2
Section 17 I
C bus (inter-IC bus)
2
C Bus Interface 2 (IIC2)
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