R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1059

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
17.7
1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.
2. Control WAIT in the I
3. In slave receive mode, even if a slave address does not match, received data is stored in
4. If 0 is written to the ICE bit in ICCRA or 1 is written to the IICRST bit in ICCRB in one of the
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Check SCLO in the I
When the start/stop conditions are issued (retransmitted) at the specific timing under the
following condition (i) or (ii), such conditions may not be output successfully. This does not
occur in other cases.
(i) When the rising of SCL falls behind the time specified in section 17.6, Bit Synchronous
(ii) When the bit synchronous circuit is activated by extending the low period of eighth and
When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave
device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This
does not occur in other cases.
ICDRR, and then the RDRF bit in ICSRL is set. To confirm whether or not the addresses
matched, see the AAS bit in the I2C bus status register (ICSR). (See figure 17.17, Sample
Flowchart for Slave Receive Mode.)
following four states, the BBSY bit in ICCRB and STOP bit in ICSR are undefined.
(1) This module is the bus master of the I2C in master transmission mode (MST = 1 and TRS
(2) This module is the bus master of the I2C in master reception mode (MST = 1 and TRS = 0
(3) This module is transmitting data in slave transmission mode (MST = 0 and TRS = 1 in
(4) This module is transmitting an acknowledgment in slave reception mode (MST = 0 and
The undefined state of BBSY in ICCRB can be exited in one of the following ways:
⎯ Input the start condition (SCL = high and SDA falling) to set BBSY to 1.
⎯ Input the stop condition (SCL = high and SDA rising) to clear BBSY to 0.
⎯ Write 1 to BBSY and 0 to SCP in ICCRB to issue the start condition with SCL = high and
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
ninth clocks, that is driven by the slave device
= 1 in ICCRA).
in ICCRA).
ICCRA).
TRS = 0 in ICCRA).
SDA = high in master transmission mode. BBSY is set to 1 when the start condition (SCL
= high and SDA falling) is output.
Usage Notes
2
C control register B (IICRB) to confirm the fall of the ninth clock.
2
C bus mode register (ICMR) to be set to 0.
Section 17 I
2
C Bus Interface 2 (IIC2)
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