R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 22

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3 Operation ........................................................................................................................... 873
14.4 Operation Timing............................................................................................................... 875
14.5 Operation with Cascaded Connection................................................................................ 879
14.6 Interrupt Sources................................................................................................................ 880
14.7 Usage Notes ....................................................................................................................... 881
Section 15 Watchdog Timer (WDT) ................................................................. 887
15.1 Features.............................................................................................................................. 887
15.2 Input/Output Pin ................................................................................................................ 888
15.3 Register Descriptions ......................................................................................................... 889
15.4 Operation ........................................................................................................................... 892
15.5 Interrupt Source ................................................................................................................. 895
15.6 Usage Notes ....................................................................................................................... 896
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14.3.1 Pulse Output.......................................................................................................... 873
14.3.2 Reset Input ............................................................................................................ 874
14.4.1 TCNT Incrementation Timing .............................................................................. 875
14.4.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 876
14.4.3 Timing of Timer Output when Compare-Match Occurs....................................... 877
14.4.4 Timing of Compare Match Clear.......................................................................... 877
14.4.5 Timing of TCNT External Reset........................................................................... 878
14.4.6 Timing of Overflow Flag (OVF) Setting .............................................................. 878
14.5.1 16-Bit Counter Mode ............................................................................................ 879
14.5.2 Compare Match Count Mode................................................................................ 879
14.6.1 Interrupt Sources and DTC Activation ................................................................. 880
14.6.2 A/D Converter Activation..................................................................................... 880
14.7.1 Contention between TCNT Write and Clear......................................................... 881
14.7.2 Contention between TCNT Write and Increment ................................................. 882
14.7.3 Contention between TCOR Write and Compare Match ....................................... 883
14.7.4 Contention between Compare Matches A and B .................................................. 884
14.7.5 Switching of Internal Clocks and TCNT Operation ............................................. 884
14.7.6 Mode Setting with Cascaded Connection ............................................................. 886
14.7.7 Module Stop Mode Setting ................................................................................... 886
14.7.8 Interrupts in Module Stop State ............................................................................ 886
15.3.1 Timer Counter (TCNT)......................................................................................... 889
15.3.2 Timer Control/Status Register (TCSR)................................................................. 889
15.3.3 Reset Control/Status Register (RSTCSR)............................................................. 891
15.4.1 Watchdog Timer Mode......................................................................................... 892
15.4.2 Interval Timer Mode............................................................................................. 894
15.6.1 Notes on Register Access ..................................................................................... 896
15.6.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 898