R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 523

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
9.4.12
The operation for ending EXDMA transfer depends on the transfer end conditions. When
EXDMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that EXDMA
transfer has ended.
(1)
When the value of EDTCR changes from 1 to 0, EXDMA transfer ends on the corresponding
channel and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this
time, a transfer end interrupt request is generated by the transfer counter and the IRF bit in
EDMDR is set to 1.
In block transfer mode, EXDMA transfer ends when the value of bits 15 to 0 in EDTCR changes
from 1 to 0.
EXDMA transfer does not end if the EDTCR value has been 0 since before the start of transfer.
(2)
If an address overflows the repeat area when a repeat area specification has been made and repeat
interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow
interrupt is requested. EXDMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF
bit in EDMDR is set to 1.
In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the
following write cycle processing is still executed.
In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,
transfer continues to the end of the block. Transfer end by means of a repeat area overflow
interrupt occurs between block-size transfers.
(3)
When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of
the EXDMA cycle in which transfer is in progress or a transfer request was accepted.
In block transfer mode, EXDMA transfer halts after completion of one-block-size transfer.
The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that
point, the value of the EDA bit will be read as 1.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Transfer End by 1 → 0 Transition of EDTCR
Transfer End by Repeat Area Overflow Interrupt
Transfer End by 0-Write to EDA Bit in EDMDR
Ending EXDMA Transfer
Section 9 EXDMA Controller (EXDMAC)
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