R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 347

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
7.13
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are four bus masters⎯the CPU, DTC, DMAC, and EXDMAC*⎯that perform read/write
operations when they have possession of the bus. Each bus master requests the bus by means of a
bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use
of the bus by means of a bus request acknowledge signal. The selected bus master then takes
possession of the bus and begins its operation.
Note: * The EXDMAC is not supported by the H8S/2425 Group.
7.13.1
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one
bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a
bus master receives the bus request acknowledge signal, it takes possession of the bus until that
signal is canceled.
The order of priority of the bus mastership is as follows:
An internal bus access by internal bus masters except the EXDMAC*
refresh, and an external bus access by the EXDMAC*
If an external bus release request, a refresh request*
master occur simultaneously, the order of priority is as follows:
As a refresh*
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.
Notes: 1. Not supported by the 5-V version.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
(High) EXDMAC*
(High) Refresh*
(High) External bus release > External access by internal bus master except EXDMAC*
2. The EXDMAC is not supported by the H8S/2425 Group.
Bus Arbitration
Operation
1
when the CBRM bit in REFCR is cleared to 0 and an external access other than to
1
> EXDMAC*
2
> DMAC > DTC > CPU (Low)
2
> External bus release (Low)
1
, and an external access by an internal bus
2
can be executed in parallel.
2
, external bus release, a
Section 7 Bus Controller (BSC)
Page 317 of 1448
2
(Low)