R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 727
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
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REALTEK
Quantity:
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Manufacturer:
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Quantity:
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H8S/2427, H8S/2427R, H8S/2425 Group
• PF2/LCAS*
• Modes 1, 2, 4, and 3, 5, 7 (EXPE = 1)
• Modes 3, 5, 7 (EXPE = 0)
Notes: 1. IRQ15-A input when the ITS15 bit in ITSR is 0.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Areas 2 to 5
SSU settings
PF2DDR
Pin function
Areas 2 to 5
SSU settings
PF2DDR
Pin function
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR*
and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR.
2. SSI0-C input when SSI0S1 and SSI0S0 = B'10 in PFCR5.
3. SSI0-C output when SSI0S1 and SSI0S0 = B'10 in PFCR5.
4. Not supported in the 5-V version.
5. Not supported in the H8S/2427 Group.
4
/DQML*
synchronous DRAM
space area is 16-bit
DQML*
LCAS*
Any DRAM/
PF2 input
bus space
5
/IRQ15-A/SSI0-C (H8S/2427 Group and H8S/2427R Group)
0
⎯
⎯
4
5
(1) in table below
output
output
PF2 input
PF2 output
8-bit bus space, or areas 2 to 5 are all normal space
(1) in table below
0
IRQ15-A interrupt input*
IRQ15-A interrupt input*
All DRAM/synchronous DRAM space areas are
1
PF2 output SSI0-C input*
⎯
1
(2) in table below
SSI0-C input*
4
of the bus controller, bits SSI0S1
0
(2) in table
1
1
below
0
2
2
(3) in table below
SSI0-C output*
Section 11 I/O Ports
SSI0-C output*
(3) in table
Page 697 of 1448
below
⎯
⎯
3
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