R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1133
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Note: Hatching boxes represent SSU internal operations.
[1]
[2]
[4]
[5]
[6]
No
Read received data in SSRDR
Read receive data in SSRDR
RDRF automatically cleared
Overrun error processing
Clear ORER in SSSR
Dummy-read SSRDR
Consecutive data
Figure 20.8 Flowchart Example of Data Reception (SSU Mode)
End reception
End reception
Initial setting
Read SSSR
RDRF = 1?
ORER = 1?
reception?
RE = 0
Start
Yes
Yes
No
Yes
No
[3]
[1]
[2]
[3], [6] Receive error processing:
[4]
[5]
Initial setting:
Specify the receive data format.
Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
To continue single reception:
When continuing single reception, wait for time of t
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
Section 20 Synchronous Serial Communication Unit (SSU)
Page 1103 of 1448
SUcyc
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