R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 485

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
(2)
In block transfer mode, the number of bytes or words specified by the block size is transferred in
response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower
16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During
transfer of a block, transfer requests for other higher-priority channels are held pending. When
transfer of one block is completed, the bus is released in the next cycle.
When the EBRE bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The ETEND signal is output for each block transfer in the EXDMA transfer cycle in which the
block ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
Caution is required when setting the repeat area overflow interrupt of the repeat area function in
block transfer mode. See section 9.4.6, Repeat Area Function, for details.
Block transfer is aborted if an NMI interrupt is generated. See section 9.4.12, Ending EXDMA
Transfer, for details.
Figure 9.8 shows an example of EXDMA transfer timing in block transfer mode.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Transfer conditions:
EDREQ
EDRAK
Bus cycle
ETEND
· Single address mode
· BGUP = 0
· Block size (EDTCR[23:16]) = 3
Block Transfer Mode
CPU
Figure 9.8 Example of Timing in Block Transfer Mode
CPU
CPU
EXDMAC
One-block transfer cycle
CPU cycle not generated
EXDMAC
Section 9 EXDMA Controller (EXDMAC)
EXDMAC
CPU
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