R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 188

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
7.2
Table 7.1 shows the pin configuration of the bus controller.
Table 7.1
Page 158 of 1448
Name
Address strobe
Address hold
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/
row address strobe 2/
row address strobe*
Chip select 3/
row address strobe 3/
column address strobe*
Input/Output Pins
Pin Configuration
1
1
Symbol
AS
AH
RD
HWR/WE*
LWR
CS0
CS1
CS2/
RAS2*
RAS*
CS3/
RAS3*
CAS*
2
2
1
1
/
/
1
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Function
Strobe signal indicating that normal space
is accessed and address output on
address bus is enabled.
Signal indicating the timing for latching the
address when the address/data
multiplexed I/O space is set.
Strobe signal indicating that normal space
is being read.
Strobe signal indicating that normal space
is written to, and upper half (D15 to D8) of
data bus is enabled or DRAM space write
enable signal.
Strobe signal indicating that normal space
is written to, and lower half (D7 to D0) of
data bus is enabled.
Strobe signal indicating that area 0 is
selected.
Strobe signal indicating that area 1 is
selected
Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM space or areas 2 to
5 are set as continuous DRAM space, or
row address strobe signal of the
synchronous DRAM when the
synchronous DRAM interface is selected.
Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM space, or column
address strobe signal of the synchronous
DRAM when the synchronous DRAM
interface is selected.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010