R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 442

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle in common register enabled mode or DMAECRS write cycle in
common register disabled mode for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
(4)
Set the DTA bit in DMABCR in common register enabled mode or the DTA bit in DMAECRS in
common register disabled mode to 1 for the channel for which the DREQ pin is selected.
Figure 8.36 shows an example of single address mode transfer activated by the DREQ pin low
level.
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Figure 8.36 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ Pin Low Level Activation Timing
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
φ
DREQ
Address
bus
DACK
DMA
control
Channel
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Idle
Minimum of 4 cycles
[1]
Bus release
Request
[2]
Request clear period
Single
[3]
Transfer source/
DMA single
destination
Acceptance resumes
Idle
Minimum of 4 cycles
[4]
Request
Bus release
[5]
Request clear period
Single
[6]
Transfer source/
DMA single
destination
Idle
Acceptance resumes
H8S/2427, H8S/2427R, H8S/2425 Group
[7]
Bus release
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010