R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 436

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
Figure 8.30 shows an example of block transfer mode transfer activated by DREQ pin low level.
φ
DREQ
Address
bus
DMA
control
Channel
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle in common register enabled mode or DMAECRF write cycle in
common register disabled mode for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
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Figure 8.30 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Idle
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Minimum of 4 cycles
Request
Bus release
[2]
Read
[3]
Transfer source
DMA read
Request clear period
Write
1 block transfer
Transfer destination
DMA write
Acceptance resumes
Dead
Minimum of 4 cycles
[4]
DMA
Request
dead
Idle
[5]
release
Bus
Read
[6]
Transfer source
DMA read
Write
H8S/2427, H8S/2427R, H8S/2425 Group
Request clear period
1 block transfer
Transfer destination
DMA write
REJ09B0565-0100 Rev. 1.00
Dead
Acceptance resumes
DMA
dead
[7]
Jul 22, 2010
Bus release
Idle