R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1265

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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H8S/2427, H8S/2427R, H8S/2425 Group
Table 26.3 Combinations of SYSCR Settings and Operation in Access to On-Chip RAM
26.2.6
When the ACSE bit in MSTPCRH is set to 1 and module stop state is set for all the on-chip
peripheral functions controlled by MSTPCR or EXMSTPCR (MSTPCR = H'FFFF, EXMSTPCR
= H'FFFF), or for all the on-chip peripheral functions except the 8-bit timer (MSTPCR = H'FFFE,
EXMSTPCR = H'FFFF), executing a SLEEP instruction while the SSBY bit in SBYCR is cleared
to 0 will cause all the on-chip peripheral functions (except the 8-bit timer and watchdog timer), the
bus controller, and the I/O ports to stop operating, and a transition to be made to all module clocks
stop mode at the end of the bus cycle.
Operation or stopping of the 8-bit timer can be selected by means of the MSTP0 bit.
To further reduce the current consumption in all module clocks stop mode, stop the modules
controlled by RMMSTPCR (RMMSTPCR = H'FFFF).
All module clocks stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15* pins),
RES pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the
normal program execution state via the exception handling state. All module clocks stop mode is
not cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Note: * IRQ8 to IRQ15 are not supported by the H8S/2425 Group.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
RAME
1
0
Register Settings
EXPE
X
1
0
All Module Clocks Stop Mode
mstp
1
0
X
X
Target for Access Description
On-chip RAM
External address
space
This area is not readable/writable and access is
prohibited.
This area is not readable/writable and access is
prohibited.
Section 26 Power-Down Modes
Page 1235 of 1448

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