R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 432

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
(5)
Set the DTA bit in DMABCR in common register enabled mode or the DTA bit in DMAECRS or
DMAECRF in common register disabled mode to 1 for the channel for which the DREQ pin is
selected.
Figure 8.27 shows an example of normal mode transfer activated by the DREQ pin falling edge.
φ
DREQ
Address
bus
DMA
control
Channel
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle in common register enabled mode or DMAECRS or DMAECRF
write cycle in common register disabled mode for setting the transfer enabled state as the starting
point.
Page 402 of 1448
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8.27 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
DREQ Pin Falling Edge Activation Timing
Idle
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Minimum of 4 cycles
Bus release
[1]
Request
[2]
Read
[3]
Request clear period
Transfer source
DMA read
Write
Transfer destination
DMA write
Acceptance resumes
Idle
Minimum of 4 cycles
[4]
Request
Bus release
[5]
Read
[6]
Transfer source
DMA read
H8S/2427, H8S/2427R, H8S/2425 Group
Request clear period
Write
REJ09B0565-0100 Rev. 1.00
Transfer destination
DMA write
Acceptance resumes
Idle
[7]
Jul 22, 2010
Bus release