R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 21

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 13 Programmable Pulse Generator (PPG) ............................................837
13.1 Features.............................................................................................................................. 837
13.2 Input/Output Pins............................................................................................................... 839
13.3 Register Descriptions ......................................................................................................... 840
13.4 Operation ........................................................................................................................... 849
13.5 Usage Notes ....................................................................................................................... 860
Section 14 8-Bit Timers (TMR).........................................................................861
14.1 Features.............................................................................................................................. 861
14.2 Register Descriptions ......................................................................................................... 864
12.10.8 Contention between TGR Read and Input Capture............................................... 831
12.10.9 Contention between TGR Write and Input Capture.............................................. 832
12.10.10 Contention between Buffer Register Write and Input Capture.......................... 833
12.10.11 Contention between Overflow/Underflow and Counter Clearing...................... 834
12.10.12 Contention between TCNT Write and Overflow/Underflow............................. 835
12.10.13 Multiplexing of I/O Pins.................................................................................... 835
12.10.14 Interrupts in Module Stop State ......................................................................... 835
13.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 840
13.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 842
13.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 843
13.3.4 PPG Output Control Register (PCR) .................................................................... 846
13.3.5 PPG Output Mode Register (PMR) ...................................................................... 847
13.4.1 Output Timing ...................................................................................................... 850
13.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 851
13.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)........... 852
13.4.4 Non-Overlapping Pulse Output............................................................................. 853
13.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 855
13.4.6 Example of Non-Overlapping Pulse Output
13.4.7 Inverted Pulse Output ........................................................................................... 858
13.4.8 Pulse Output Triggered by Input Capture ............................................................. 859
13.5.1 Module Stop Function Setting .............................................................................. 860
13.5.2 Operation of Pulse Output Pins............................................................................. 860
14.2.1 Timer Counter (TCNT)......................................................................................... 865
14.2.2 Time Constant Register A (TCORA).................................................................... 865
14.2.3 Time Constant Register B (TCORB) .................................................................... 865
14.2.4 Timer Control Register (TCR).............................................................................. 866
14.2.5 Timer Counter Control Register (TCCR) ............................................................. 867
14.2.6 Timer Control/Status Register (TCSR)................................................................. 869
(Example of Four-Phase Complementary Non-Overlapping Output) .................. 856
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