R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 548

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Section 10 Data Transfer Controller (DTC)
10.5.1
Transfer Information Read Skip Function
By setting the RRS bit in DTCCR, the vector address read and transfer information read can be
skipped. The current DTC vector number is always compared with the vector number of previous
activation. If the vector numbers match when the RRS bit is 1, a DTC data transfer is performed
without reading the vector address and transfer information. If the previous activation is a chain
transfer or the transfer counter is 0, the vector address read and transfer information read are
always performed. Figure 10.6 shows the timing chart of transfer information read skip.
To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the
vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is
cleared to 0 or the DTCE bit is cleared to 0, the stored vector number is discarded, and the updated
vector table and transfer information are read at the next activation.
Clock
DTC activation
(1)
(2)
request
DTC request
Transfer
information
read skip
Address
R
W
R
W
Vector
Transfer
Data
Transfer
Data
Transfer
read
information
transfer
information
transfer
information
read
write
write
Note: Transfer information read is skipped when the activation sources (vector numbers) of (1) and (2) are the same while RRS = 1.
Figure 10.6 Transfer Information Read Skip Timing
Page 518 of 1448
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010