R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 89

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
2.4.5
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32-
bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.
2.4.6
When the reset exception handling loads the start address from the vector address, PC is
initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However,
the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is
undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a
reset.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
2
1
0
Multiply-Accumulate Register (MAC)
Initial Values of CPU Internal Registers
Bit Name
Z
V
C
Initial Value
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
Description
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
•
•
The carry flag is also used as a bit accumulator
by bit manipulation instructions.
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to indicate a
carry
Page 59 of 1448
Section 2 CPU