R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1128
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 Synchronous Serial Communication Unit (SSU)
Page 1098 of 1448
Figure 20.5 (3) Example of Transmission Operation (SSU Mode) When 24-Bit Data Length
When 32-Bit Data Length is Selected (SSTDR0, SSTDR1, SSTDR2 and SSTDR3 are Valid)
is Selected (SSTDR0, SSTDR1, and SSTDR2 are Valid) with CPOS = 0 and CPHS = 0
User operation
LSI operation
Figure 20.5 (4) Example of Transmission Operation (SSU Mode)
(MSB first)
(LSB first)
SSCK
TDRE
TEND
User operation
SSO
SSO
SCS
LSI operation
(MSB first)
(LSB first)
SSCK
TDRE
TEND
SSO
SSO
SCS
Data written to SSTDR0, SSTDR1, and SSTDR2
Data written to SSTDR0, SSTDR1, SSTDR2 and SSTDR3
with CPOS = 0 and CPHS = 0
Bit
Bit
0
7
Bit
Bit
Bit
Bit
0
7
1
6
SSTDR3
SSTDR2
SSTDR0
SSTDR0
to
to
to
to
Bit
Bit
Bit
Bit
0
7
6
1
Bit
Bit
Bit
Bit
0
7
7
0
SSTDR2
SSTDR1
Bit
Bit
to
to
0
7
TXI interrupt generated TEI interrupt generated
TXI interrupt generated
1 frame
1 frame
Bit
Bit
0
Bit
Bit
7
1
6
SSTDR1
SSTDR1
Bit
Bit
0
7
to
to
SSTDR1
SSTDR2
to
to
Bit
Bit
6
1
Bit
Bit
Bit
Bit
7
0
7
0
Bit
Bit
0
7
Bit
Bit
0
7
SSTDR0
SSTDR3
to
to
Bit
Bit
H8S/2427, H8S/2427R, H8S/2425 Group
1
6
SSTDR0
SSTDR2
Bit
Bit
TEI interrupt generated
7
0
to
to
Bit
Bit
6
1
Bit
Bit
7
0
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
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