R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 16

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.5
9.6
Section 10 Data Transfer Controller (DTC)......................................................499
10.1 Features.............................................................................................................................. 499
10.2 Register Descriptions ......................................................................................................... 501
10.3 Activation Sources............................................................................................................. 509
10.4 Location of Register Information and DTC Vector Table ................................................. 510
10.5 Operation ........................................................................................................................... 515
10.6 Procedures for Using DTC................................................................................................. 527
10.7 Examples of Use of the DTC ............................................................................................. 528
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9.4.11 Examples of Operation Timing in Each Mode ..................................................... 479
9.4.12 Ending EXDMA Transfer..................................................................................... 493
9.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 494
Interrupt Sources................................................................................................................ 495
Usage Notes ....................................................................................................................... 497
10.2.1 DTC Mode Register A (MRA) ............................................................................. 501
10.2.2 DTC Mode Register B (MRB).............................................................................. 503
10.2.3 DTC Source Address Register (SAR)................................................................... 503
10.2.4 DTC Destination Address Register (DAR)........................................................... 504
10.2.5 DTC Transfer Count Register A (CRA) ............................................................... 504
10.2.6 DTC Transfer Count Register B (CRB)................................................................ 504
10.2.7 DTC Enable Registers A to I (DTCERA to DTCERI) ......................................... 505
10.2.8 DTC Vector Register (DTVECR)......................................................................... 505
10.2.9 DTC Vector Base Register (DTCVBR)................................................................ 506
10.2.10 DTC Control Register (DTCCR) .......................................................................... 506
10.5.1 Transfer Information Read Skip Function ............................................................ 518
10.5.2 Transfer Information Writeback Skip Function.................................................... 519
10.5.3 Normal Mode........................................................................................................ 520
10.5.4 Repeat Mode......................................................................................................... 521
10.5.5 Block Transfer Mode ............................................................................................ 522
10.5.6 Chain Transfer ...................................................................................................... 523
10.5.7 Interrupt Sources................................................................................................... 524
10.5.8 Operation Timing.................................................................................................. 524
10.5.9 Number of DTC Execution States ........................................................................ 525
10.6.1 Activation by Interrupt.......................................................................................... 527
10.6.2 Activation by Software ......................................................................................... 527
10.7.1 Normal Mode........................................................................................................ 528
10.7.2 Chain Transfer ...................................................................................................... 529
10.7.3 Chain Transfer when Counter = 0......................................................................... 530
10.7.4 Software Activation .............................................................................................. 532