R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1122

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 20 Synchronous Serial Communication Unit (SSU)
20.4.3
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 20.3
shows the relationship.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 20.3 (1)). The SSU
transmits serial data from the SSI pin and receives serial data from the SSO pin when operating
with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 20.3 (2)).
The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode
when operating with BIDE = 1 (bidirectional mode) (see figures 20.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function
as an input pin when MSS = 0 (see figures 20.3 (5) and (6)).
Page 1092 of 1448
(1) When SSUMS = 0, BIDE = 0 (standard mode),
(4) When SSUMS = 0, BIDE = 1 (bidirectional mode),
(5) When SSUMS = 1 and MSS = 1
Figure 20.3 Relationship between Data Input/Output Pins and Shift Register
MSS = 1, TE = 1, and RE = 1
MSS = 1, and either TE or RE = 1
Relationship between Data Input/Output Pins and Shift Register
Shift register
Shift register
Shift register
(SSTRSR)
(SSTRSR)
(SSTRSR)
SSCK
SSO
SSI
SSCK
SSO
SSI
SSCK
SSO
SSI
(2) When SSUMS = 0, BIDE = 0 (standard mode),
(3) When SSUMS = 0, BIDE = 1 (bidirectional mode),
(6) When SSUMS = 1 and MSS = 0
MSS = 0, TE = 1, and RE = 1
MSS = 0, and either TE or RE = 1
Shift register
Shift register
Shift register
(SSTRSR)
(SSTRSR)
(SSTRSR)
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
SSCK
SSO
SSI
SSCK
SSO
SSI
SSCK
SSO
SSI
Jul 22, 2010