R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 224

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Section 7 Bus Controller (BSC)
Table 7.2
(n = 0 to 7)
(4)
RDNCR can be used to select either of two negation timings (at the end of the read cycle or one
half-state before the end of the read cycle) for the read strobe (RD) used in the basic bus interface
space.
(5)
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. CSACR can be used to insert states in which only the
CS, AS, and address signals are asserted before and after a basic bus space access cycle.
Page 194 of 1448
ABWCR
ABWn
0
1
Read Strobe Timing
Chip Select (CS) Assertion Period Extension States
Bus Specifications for Each Area (Basic Bus Interface)
ASTCR
ASTn
0
1
0
1
Wn2
0
1
0
1
WTCRA, WTCRB
Wn1
0
1
0
1
0
1
0
1
Wn0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bus Width
16
8
Bus Specifications (Basic Bus Interface)
H8S/2427, H8S/2427R, H8S/2425 Group
Access
States
2
3
2
3
REJ09B0565-0100 Rev. 1.00
Program Wait
States
0
0
1
2
3
4
5
6
7
0
0
1
2
3
4
5
6
7
Jul 22, 2010

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