R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 494

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 9 EXDMA Controller (EXDMAC)
(1)
If transfer requests for different channels are issued during a transfer operation, the highest-
priority channel (excluding the currently transferring channel) is selected. The selected channel
begins transfer after the currently transferring channel releases the bus. If there is a bus request
from a bus master other than the EXDMAC at this time, a cycle for the other bus master is
initiated. If there is no other bus request, the bus is released for one cycle.
Channel switching does not take place during a burst transfer or a block transfer of a single block.
Figure 9.13 shows a case in which transfer requests for channels 2 and 3 are issued
simultaneously. The example shown in the figure illustrates the handling of external requests in
the cycle steal mode.
(2)
If transfer requests for different channels are issued during a transfer in auto request cycle steal
mode, the operation depends on the channel priority. If the channel that made the transfer request
is of higher priority than the channel currently performing transfer, the channel that made the
transfer request is selected.
If the channel that made the transfer request is of lower priority than the channel currently
performing transfer, that channel’s transfer request is held pending, and the currently transferring
channel remains selected.
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Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode)
Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode
φ
Address bus
EXDMA control
Channel 2
Channel 3
Figure 9.13 Example of Channel Priority Timing
Idle
Request
Request cleared
held
Channel 2
Selected
Channel 2 transfer
Request cleared
Channel 2
Channel 3
release
Bus
H8S/2427, H8S/2427R, H8S/2425 Group
Channel 3 transfer
Channel 3
REJ09B0565-0100 Rev. 1.00
release
Bus
Jul 22, 2010