R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 451

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
8.6
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8.11
shows the interrupt sources and their priority order.
Table 8.11 Interrupt Sources and Priority Order
• Common register enabled mode (DMCOMMD = 1)
• Common register disabled mode (DMCOMMD = 0)
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCR in
common register enabled mode or the DTIE bit in DMAECRS or DMAECRF in common register
disabled mode for the corresponding channel, and interrupts from each source are sent to the
interrupt controller independently. The priority of transfer end interrupts on each channel is
decided by the interrupt controller, as shown in table 8.11.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Interrupt Name
DMTEND0/DMTEND4
DMTEND1/DMEEND4
DMTEND2/DMTEND5
DMTEND3/DMEEND5
Interrupt Name
DMTEND0
DMTEND1
DMTEND4
DMEEND4
DMTEND2
DMTEND3
DMTEND5
DMEEND5
Interrupt Sources
Short Address Mode
Interrupt due to end of
transfer on channel 0
Interrupt due to end of
transfer on channel 1
Interrupt due to end of
transfer on channel 2
Interrupt due to end of
transfer on channel 3
Interrupt Source
Interrupt due to end of transfer on channel 0
Interrupt due to end of transfer on channel 1
Interrupt due to end of transfer on channel 4
Interrupt due to break in transfer on channel 4
Interrupt due to end of transfer on channel 2
Interrupt due to end of transfer on channel 3
Interrupt due to end of transfer on channel 5
Interrupt due to break in transfer on channel 5
Interrupt Source
Full Address Mode
Interrupt due to end of
transfer on channel 4
Interrupt due to break in
transfer on channel 4
Interrupt due to end of
transfer on channel 5
Interrupt due to break in
transfer on channel 5
Section 8 DMA Controller (DMAC)
Interrupt
Priority Order
High
Low
Interrupt
Priority Order
High
Low
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