R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1041
R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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H8S/2427, H8S/2427R, H8S/2425 Group
17.4
17.4.1
Figure 17.3 shows the I
following a start condition always consists of 8 bits.
Legend:
S:
SLA:
R/W:
A:
DATA: Transferred data
P:
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
SDA
SCL
(a) I
(b) I
S
S
1
1
2
2
C bus format
C bus format (start condition retransmission)
S
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
Acknowledge. The receiving device drives SDA to low.
Stop condition. The master device drives SDA from low to high while SCL is high.
Operation
I
2
C Bus Format
SLA
SLA
7
7
SLA
1-7
1
1
R/W
R/W
1
1
2
C bus formats. Figure 17.4 shows the I
R/W
8
A
A
1
1
A
9
DATA
DATA
Figure 17.3 I
n1
Figure 17.4 I
n
m1
A
1
1-7
A/A
DATA
1
m
2
C Bus Formats
2
S
1
C Bus Timing
8
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
SLA
7
A/A
9
A
1
1
2
C bus timing. The first frame
R/W
P
1
1
1-7
m: transfer frame count
(m ≥ 1)
Section 17 I
n: transfer bit count
(n = 1 to 8)
A
1
DATA
DATA
8
n2
m2
2
C Bus Interface 2 (IIC2)
Page 1011 of 1448
A
9
A/A
1
P
1
P
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