R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 346

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
Figure 7.97 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
Note: The synchronous DRAM interface is not supported by the H8S/2427 Group and H8S/2425
Page 316 of 1448
DQMU, DQML
Precharge-sel
Address bus
Figure 7.97 Bus Release State Transition Timing when Synchronous DRAM Interface
SDRAMφ
Data bus
BREQO
BREQ
BACK
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
RAS
CAS
CKE
WE
Group.
Low level of BREQ signal is sampled at the rising edge of φ.
PALL command is issued.
Bus control signal returns high at the end of external space access cycle.
At least two states from sampling of BREQ signal.
BACK signal is driven low, releasing bus to an external bus master.
BREQ signal state is sampled even in external bus released state.
High level of BREQ signal is sampled.
BACK signal is driven high, completing the external bus release cycle.
When there is an external access or a refresh request from an internal bus master
in external bus released state while the BREQOE bit is set to 1, BREQO signal goes low.
BREQO signal goes high 1.5 states after the rising edge of BACK signal in most cases.
If BREQO signal is asserted because of auto-refreshing request, it is kept low until the auto-refresh cycle starts.
[1]
NOP
access cycle
External
T
1
T
2
[2]
PALL
[3]
NOP
[4]
[5]
External bus released state
[8]
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[6]
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
[7]
NOP
Jul 22, 2010
[9]
CPUcycle