R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 376

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
8.3.11
DMAECRF controls the operation of DMAC channels 4 and 5.
• DMAECRF4 and DMAECRF5
Page 346 of 1448
Bit
7
6
Bit Name
DTME
DMIE
DMA Enable Control Register F (DMAECRF)
0
0
Initial Value
R/W
R/W
R/W
Description
Data Transfer Master Enable
Together with the DTE1 bit, this bit enables or
disables data transfer. When both the DTME1 bit
and DTE1 bit are set to 1, transfer is enabled.
If an NMI interrupt is generated in the middle of a
burst mode transfer, the DTME bit is cleared to 0,
the transfer is interrupted, and bus mastership is
passed to the CPU. When the DTME bit is
subsequently set to 1 again, the interrupted
transfer is resumed. In block transfer mode,
however, the DTME bit is not cleared by an NMI
interrupt, and transfer is not interrupted.
[Clearing conditions]
•
•
•
[Setting condition]
•
Data Transfer Interrupt Enable
Enables or disables an interrupt to the CPU or
DTC when transfer on the relevant channel has
been interrupted. If the DTME bit is cleared to 0
when DMIE = 1, the DMAC regards this as
indicating the break in a transfer, and issues a
transfer break interrupt request to the CPU or
DTC.
A transfer break interrupt can be canceled either
by clearing the DMIE bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME bit to 1.
When initialization is performed
When NMI is input in burst mode
When 0 is written to the DTME1 bit
When 1 is written to DTME after reading
DTME = 0
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010