R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 563

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
10.8
10.8.1
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting the module stop
state. The module stop state cannot be set while the DTC is activated. For details, refer to section
26, Power-Down Modes.
10.8.2
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0 and the pertinent MSTP bit in
RMMSTPCR must not be set to 1.
10.8.3
The transfer information start address to be specified in the vector table should be address 4n. If an
address other than address 4n is specified, the lowest 2 bits of the address are regarded as 0s.
10.8.4
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
10.8.5
When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer
counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has
priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer
counter reaches 0.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Usage Notes
Module Stop Function Setting
On-Chip RAM
Transfer Information Start Address
DTCE Bit Setting
DMAC Transfer End Interrupt
Section 10 Data Transfer Controller (DTC)
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