R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1030

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 17 I
17.3.1
ICCRA is an 8-bit readable/writable register that enables or disables the I
transmission or reception, and selects master or slave mode, transmission or reception, and
transfer clock frequency in master mode.
Page 1000 of 1448
Bit
7
6
5
4
Bit Name
ICE
RCVD
MST
TRS
I
2
C Bus Interface 2 (IIC2)
2
C Bus Control Register A (ICCRA)
0
0
0
0
Initial Value
R/W
R/W
R/W
R/W
R/W
Description
I
0: Disables SCL/SDA outputs. (Inputs to SCL/SDA
1: This bit is enabled for transfer operations. (SCL
Reception Disable
This bit enables or disables the next operation
when TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
When arbitration is lost in master mode, MST and
TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of
the TRS bit should be made between transfer
frames. In addition, TRS is set to 1 automatically
in slave receive mode if the seventh bit of the start
condition matches the slave address set in SAR
and the eighth bit is set to 1.
Operating modes are described below according
to MST and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
2
C Bus Interface Enable
are enabled.)
and SDA pins are bus drive state.)
H8S/2427, H8S/2427R, H8S/2425 Group
2
C bus interface, controls
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010