R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 413

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
8.5.5
Single address mode can only be specified for channels 1 and 3 in common register enabled mode,
or for channels 0 and 1 in common register disabled mode. Single address mode can be specified
by setting the SAE bit in DMABCR in common register enabled mode or the SAE bit in
DMAECRS in common register disabled mode to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACRS.
Table 8.7 summarizes register functions in single address mode.
Table 8.7
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Register
23
15
Single Address Mode
DACK pin
Register Functions in Single Address Mode
ETCR
MAR
0
0
Source
address
register
Write
strobe
Transfer counter
DTDIR = 0 DTDIR = 1 Initial Setting
Function
Destination
address
register
Read
strobe
Start address of
transfer destination
or transfer source
(Set automatically
by SAE bit in
DMABCRH or
DMAECRS; IOAR
is invalid)
Number of transfers See sections 8.5.2,
Section 8 DMA Controller (DMAC)
Operation
See sections 8.5.2,
Sequential Mode,
8.5.3, Idle Mode,
and 8.5.4, Repeat
Mode.
Strobe for external
device
Sequential Mode,
8.5.3, Idle Mode,
and 8.5.4, Repeat
Mode.
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