R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 13

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.7
7.8
7.9
7.10 Idle Cycle........................................................................................................................... 292
7.11 Write Data Buffer Function ............................................................................................... 312
7.6.8
DRAM Interface ................................................................................................................ 227
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10 Byte Access Control ............................................................................................. 239
7.7.11 Burst Operation..................................................................................................... 240
7.7.12 Refresh Control..................................................................................................... 245
7.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 251
Synchronous DRAM Interface........................................................................................... 255
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
7.8.7
7.8.8
7.8.9
7.8.10 Bus Cycle Control in Write Cycle ........................................................................ 266
7.8.11 Byte Access Control ............................................................................................. 267
7.8.12 Burst Operation..................................................................................................... 270
7.8.13 Refresh Control..................................................................................................... 274
7.8.14 Mode Register Setting of Synchronous DRAM.................................................... 282
7.8.15 DMAC and EXDMAC Single Address Transfer Mode
Burst ROM Interface.......................................................................................................... 289
7.9.1
7.9.2
7.9.3
7.10.1 Operation .............................................................................................................. 292
7.10.2 Pin States in Idle Cycle......................................................................................... 311
Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 225
Setting DRAM Space............................................................................................ 227
Address Multiplexing ........................................................................................... 228
Data Bus ............................................................................................................... 228
Pins Used for DRAM Interface............................................................................. 229
Basic Timing......................................................................................................... 230
Column Address Output Cycle Control ................................................................ 231
Row Address Output State Control....................................................................... 233
Precharge State Control ........................................................................................ 235
Wait Control ......................................................................................................... 236
Setting Continuous Synchronous DRAM Space................................................... 255
Address Multiplexing ........................................................................................... 256
Data Bus ............................................................................................................... 257
Pins Used for Synchronous DRAM Interface....................................................... 257
Synchronous DRAM Clock .................................................................................. 259
Basic Timing......................................................................................................... 259
CAS Latency Control............................................................................................ 261
Row Address Output State Control....................................................................... 263
Precharge State Count........................................................................................... 264
and Synchronous DRAM Interface....................................................................... 283
Basic Timing......................................................................................................... 289
Wait Control ......................................................................................................... 291
Write Access......................................................................................................... 291
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