R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 367

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
8.3.5
DMAECRS controls the operation of DMAC channels 0, 1, 2, and 3.
• DMAECRS0, DMAECRS1, DMAECRS2, and DMAECRS3
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7, 6
5
Bit Name
⎯
DTE
DMA Enable Control Register S (DMAECRS)
Initial Value
All 0
0
R/W
⎯
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Data Transfer Enable
This bit is used to enable or disable the DMA data
transfer by the activation source selected by the
DTF3 to DTF0 bits in DMACRS.
When DTE = 0, data transfer is disabled and the
activation source is ignored. If the activation
source is an internal interrupt, an interrupt request
is issued to the CPU or DTC. If the DTE bit is
cleared to 0 when DTIE = 1, the DMAC regards
this as indicating the end of a transfer, and issues
a transfer end interrupt request to the CPU or
DTC.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation
source. When a request is issued by the activation
source, transfer is executed.
[Clearing conditions]
⎯ When initialization is performed
⎯ When the specified number of transfers have
⎯ When 0 is written to the DTE bit to forcibly
[Setting condition]
⎯ When 1 is written to the DTE bit after reading
been completed in a transfer mode other than
repeat mode
suspend the transfer, or for a similar reason
DTE = 0
Section 8 DMA Controller (DMAC)
Page 337 of 1448