R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 12

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC) ........................................................................ 155
7.1
7.2
7.3
7.4
7.5
7.6
Page xii of xxx
Features.............................................................................................................................. 155
Input/Output Pins............................................................................................................... 158
Register Descriptions ......................................................................................................... 161
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 DRAM Access Control Register (DRACCR)....................................................... 185
7.3.11 Refresh Control Register (REFCR) ...................................................................... 188
7.3.12 Refresh Timer Counter (RTCNT)......................................................................... 191
7.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 191
Bus Control........................................................................................................................ 192
7.4.1
7.4.2
7.4.3
7.4.4
Basic Bus Interface ............................................................................................................ 198
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
Address/Data Multiplexed I/O Interface............................................................................ 213
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
Bus Width Control Register (ABWCR)................................................................ 162
Access State Control Register (ASTCR) .............................................................. 162
Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL) ........................................... 163
Read Strobe Timing Control Register (RDNCR) ................................................. 169
CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 171
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 173
Bus Control Register (BCR) ................................................................................. 174
Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 176
DRAM Control Register (DRAMCR) .................................................................. 177
Area Division........................................................................................................ 192
Bus Specifications ................................................................................................ 193
Memory Interfaces................................................................................................ 195
Chip Select Signals ............................................................................................... 197
Data Size and Data Alignment.............................................................................. 198
Valid Strobes ........................................................................................................ 200
Basic Timing......................................................................................................... 200
Wait Control ......................................................................................................... 209
Read Strobe (RD) Timing..................................................................................... 210
Extension of Chip Select (CS) Assertion Period................................................... 212
Setting Address/Data Multiplexed I/O Space ....................................................... 213
Address/Data Multiplexing................................................................................... 213
Data Bus ............................................................................................................... 214
Address Hold Signal ............................................................................................. 214
Basic Timing......................................................................................................... 215
Wait Control ......................................................................................................... 223
Read Strobe (RD) Timing..................................................................................... 224