R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1116

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 20 Synchronous Serial Communication Unit (SSU)
Page 1086 of 1448
Bit
0
Bit Name
CE
Initial
Value
0
R/W
R/W
Description
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master device).
If the SCS pin level changes to 1 with SSUMS = 0
(SSU mode) and MSS = 0 (slave device), an
incomplete error occurs because it is determined that a
master device has terminated the transfer. Data
reception does not continue while the CE bit is set to 1.
Serial transmission also does not continue. Reset the
SSU internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting condition]
•
•
[Clearing condition]
•
When a low level is input to the SCS pin in master
device (the MSS bit in SSCRH is set to 1)
When the SCS pin is changed to 1 during transfer in
slave device (the MSS bit in SSCRH is cleared to 0)
When writing 0 after reading CE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010