R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 287

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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H8S/2427, H8S/2427R, H8S/2425 Group
7.8.3
If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous
DRAM space is set to 1, areas 2 to 5 are designated as 8-bit continuous synchronous DRAM
space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM
space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM
can be connected directly.
In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is
enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of
the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 7.5.1, Data
Size and Data Alignment.
7.8.4
Table 7.10 shows pins used for the synchronous DRAM interface and their functions.
Set the OEE bit in DRAMCR to 1 when the CKE signal is output.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Data Bus
Pins Used for Synchronous DRAM Interface
Section 7 Bus Controller (BSC)
Page 257 of 1448

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