R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 552

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer:
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Section 10 Data Transfer Controller (DTC)
10.5.5
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 10.7 lists the register function in block
transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. Once the specified number of transfers has ended, a CPU interrupt is requested.
Table 10.7 Register Function in Block Transfer Mode
Page 522 of 1448
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
SAR
or
DAR
Block Transfer Mode
Figure 10.9 Memory Mapping in Block Transfer Mode
Nth block
First block
DAR
CRAH
CRAL
CRB
Abbreviation
SAR
Transfer
Block area
Function
Designates source address
Designates destination address
Holds block size
Designates block size count
Designates transfer count
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
DAR
or
SAR
Jul 22, 2010

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