R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1240

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Section 25 Clock Pulse Generator
25.1.2
PLLCR sets the frequency multiplication factor used by the system-clock PLL circuit.
Care must be taken when writing to this register. For details, see section 25.3, System-Clock PLL
Circuit and Divider.
Page 1210 of 1448
Bit
7 to 4
3
2
1
0
Bit Name
STC1
STC0
PLL Control Register (PLLCR)
Initial Value
All 0
0
0
0
0
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Reserved
This bit is always read as 0 and cannot be
modified.
Frequency Multiplication Factor for System-
Clock PLL Circuit and System Clock Divider
Setting
The STC bits specify the frequency
multiplication factor and dividing ratio with
respect to the oscillator frequency.
00: × 1
01: × 2
10: Setting prohibited
11: 1/2
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010

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