R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 456

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Section 8 DMA Controller (DMAC)
TEND Output
(4)
In common register enabled mode, the TEND output of channels 1 and 4 are switched by the
settings of bits RSEL1 and RSEL4 in DRSEL, and the TEND output of channels 3 and 5 are
switched by the settings of bits RSEL3 and RSEL5 in DRSEL.
In common register disabled mode, the TEND output of channels 0 and 4 are switched by the
setting of bit DMA_SEL0 in PFCR3, and the TEND output of channels 1 and 5 are switched by
the setting of bit DMA_SEL1 in PFCR3.
DMA setting should not be made while switching between common register enabled mode and
common register disabled mode.
If the last transfer cycle is for an internal address, note that even if low-level output at the TEND
pin has been set, a low level may not be output at the TEND pin under the following external bus
conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed
in parallel.
1
1. EXDMAC cycle*
2. Write cycle with write buffer mode enabled
3. DMAC single address cycle for a different channel with write buffer mode enabled
4. Bus release cycle
5. CBR refresh cycle
Figure 8.45 shows an example in which a low level is not output from the TEND pin in case 2
above.
If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in
synchronization with the bus cycle.
2
However, if the last transfer cycle and a CBR refresh*
occur simultaneously, note that although
and the last transfer cycle may be executed consecutively, TEND may also go
2
the CBR refresh*
2
low in this case for the refresh cycle*
.
Notes: 1. Not supported by the H8S/2425 Group.
2. Not supported in the 5-V version.
Page 426 of 1448
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010