R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1141

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Note: Hatching boxes represent SSU internal operations.
[1]
[3]
[4]
No
Read received data in SSRDR
Read receive data in SSRDR
RDRF automatically cleared
Overrun error processing
Consecutive data reception?
Clear ORER in SSSR
End reception
End reception
Initial setting
Read SSSR
RDRF = 1?
ORER = 1?
RE = 0
Start
Figure 20.16 Flowchart Example of Data Reception
Yes
Yes
No
(Clock Synchronous Communication Mode)
Yes
No
[2]
[1]
[2], [4] Receive error processing:
[3]
Initial setting:
Specify the receive data format.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
Section 20 Synchronous Serial Communication Unit (SSU)
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