R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 243

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Both extension state T
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T
register, and for the T
7.6
If areas 6 and 7 of the external address space are specified as address/data multiplexed I/O space
in this LSI, the address/data multiplexed I/O interfacing can be performed. In the address/data
multiplexed I/O interface, peripheral LSIs that require address/data multiplexing can be connected
directly to this LSI.
7.6.1
In the address/data multiplexed I/O interface, areas 6 and 7 are designated as the address/data
multiplexed I/O space by setting the MPXE bit in MPXCR to 1.
7.6.2
With the address/data multiplexed I/O space, the data bus and address bus are multiplexed. Table
7.4 shows the relation between the bus width and corresponding address output.
Table 7.4
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bus
Width
8 bits
16 bits
Cycle
Address
Data
Address
Data
Address/Data Multiplexed I/O Interface
Setting Address/Data Multiplexed I/O Space
Address/Data Multiplexing
Multiplexed Address/Data
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
A7
D15
A15
D15
t
h
A6
D14
A14
D14
state with the lower 8 bits (CSXT7 to CSXT0).
inserted before the basic bus cycle and extension state T
A5
D13
A13
D13
A4
D12
A12
D12
h
state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
A3
D11
A11
D11
A2
D10
A10
D10
A1
D9
A9
D9
A0
D8
A8
D8
Data Pins
⎯
⎯
A7
D7
⎯
⎯
A6
D6
⎯
⎯
A5
D5
Section 7 Bus Controller (BSC)
⎯
⎯
A4
D4
⎯
⎯
A3
D3
t
inserted after the
⎯
⎯
A2
D2
Page 213 of 1448
⎯
⎯
A1
D1
⎯
⎯
A0
D0